drm/radeon: dpm updates for KV
This updates dpm support for KV asics. Notably there are some changes in acp handling and forcing performance levels. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
Родитель
8c5c6fad61
Коммит
136de91ea7
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@ -40,6 +40,7 @@ static int kv_calculate_dpm_settings(struct radeon_device *rdev);
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static void kv_enable_new_levels(struct radeon_device *rdev);
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static void kv_program_nbps_index_settings(struct radeon_device *rdev,
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struct radeon_ps *new_rps);
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static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
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static int kv_set_enabled_levels(struct radeon_device *rdev);
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static int kv_force_dpm_highest(struct radeon_device *rdev);
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static int kv_force_dpm_lowest(struct radeon_device *rdev);
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@ -519,7 +520,7 @@ static int kv_set_dpm_boot_state(struct radeon_device *rdev)
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static void kv_program_vc(struct radeon_device *rdev)
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{
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WREG32_SMC(CG_FTV_0, 0x3FFFC000);
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WREG32_SMC(CG_FTV_0, 0x3FFFC100);
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}
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static void kv_clear_vc(struct radeon_device *rdev)
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@ -638,7 +639,10 @@ static int kv_force_lowest_valid(struct radeon_device *rdev)
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static int kv_unforce_levels(struct radeon_device *rdev)
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{
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return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
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if (rdev->family == CHIP_KABINI)
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return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
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else
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return kv_set_enabled_levels(rdev);
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}
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static int kv_update_sclk_t(struct radeon_device *rdev)
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@ -1076,6 +1080,13 @@ static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
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PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
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}
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static void kv_reset_acp_boot_level(struct radeon_device *rdev)
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{
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struct kv_power_info *pi = kv_get_pi(rdev);
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pi->acp_boot_level = 0xff;
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}
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static void kv_update_current_ps(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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@ -1190,6 +1201,8 @@ int kv_dpm_enable(struct radeon_device *rdev)
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return ret;
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}
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kv_reset_acp_boot_level(rdev);
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if (rdev->irq.installed &&
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r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
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ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
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@ -1448,6 +1461,39 @@ static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
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return kv_enable_samu_dpm(rdev, !gate);
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}
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static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
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{
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u8 i;
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struct radeon_clock_voltage_dependency_table *table =
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&rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
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for (i = 0; i < table->count; i++) {
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if (table->entries[i].clk >= 0) /* XXX */
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break;
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}
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if (i >= table->count)
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i = table->count - 1;
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return i;
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}
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static void kv_update_acp_boot_level(struct radeon_device *rdev)
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{
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struct kv_power_info *pi = kv_get_pi(rdev);
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u8 acp_boot_level;
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if (!pi->caps_stable_p_state) {
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acp_boot_level = kv_get_acp_boot_level(rdev);
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if (acp_boot_level != pi->acp_boot_level) {
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pi->acp_boot_level = acp_boot_level;
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kv_send_msg_to_smc_with_parameter(rdev,
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PPSMC_MSG_ACPDPM_SetEnabledMask,
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(1 << pi->acp_boot_level));
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}
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}
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}
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static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
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{
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struct kv_power_info *pi = kv_get_pi(rdev);
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@ -1459,7 +1505,7 @@ static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
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if (pi->caps_stable_p_state)
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pi->acp_boot_level = table->count - 1;
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else
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pi->acp_boot_level = 0;
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pi->acp_boot_level = kv_get_acp_boot_level(rdev);
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ret = kv_copy_bytes_to_smc(rdev,
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pi->dpm_table_start +
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@ -1769,6 +1815,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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return ret;
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}
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#endif
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kv_update_acp_boot_level(rdev);
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kv_update_sclk_t(rdev);
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kv_enable_nb_dpm(rdev);
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}
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@ -1800,12 +1847,23 @@ void kv_dpm_setup_asic(struct radeon_device *rdev)
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void kv_dpm_reset_asic(struct radeon_device *rdev)
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{
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kv_force_lowest_valid(rdev);
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kv_init_graphics_levels(rdev);
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kv_program_bootup_state(rdev);
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kv_upload_dpm_settings(rdev);
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kv_force_lowest_valid(rdev);
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kv_unforce_levels(rdev);
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struct kv_power_info *pi = kv_get_pi(rdev);
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if (rdev->family == CHIP_KABINI) {
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kv_force_lowest_valid(rdev);
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kv_init_graphics_levels(rdev);
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kv_program_bootup_state(rdev);
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kv_upload_dpm_settings(rdev);
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kv_force_lowest_valid(rdev);
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kv_unforce_levels(rdev);
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} else {
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kv_init_graphics_levels(rdev);
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kv_program_bootup_state(rdev);
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kv_freeze_sclk_dpm(rdev, true);
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kv_upload_dpm_settings(rdev);
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kv_freeze_sclk_dpm(rdev, false);
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kv_set_enabled_level(rdev, pi->graphics_boot_level);
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}
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}
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//XXX use sumo_dpm_display_configuration_changed
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@ -1870,7 +1928,10 @@ static int kv_force_dpm_highest(struct radeon_device *rdev)
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break;
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}
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return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
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if (rdev->family == CHIP_KABINI)
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return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
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else
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return kv_set_enabled_level(rdev, i);
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}
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static int kv_force_dpm_lowest(struct radeon_device *rdev)
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@ -1887,7 +1948,10 @@ static int kv_force_dpm_lowest(struct radeon_device *rdev)
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break;
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}
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return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
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if (rdev->family == CHIP_KABINI)
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return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
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else
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return kv_set_enabled_level(rdev, i);
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}
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static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
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@ -2033,12 +2097,12 @@ static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
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ps->dpmx_nb_ps_lo = 0x1;
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ps->dpmx_nb_ps_hi = 0x0;
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} else {
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ps->dpm0_pg_nb_ps_lo = 0x1;
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ps->dpm0_pg_nb_ps_lo = 0x3;
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ps->dpm0_pg_nb_ps_hi = 0x0;
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ps->dpmx_nb_ps_lo = 0x2;
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ps->dpmx_nb_ps_hi = 0x1;
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ps->dpmx_nb_ps_lo = 0x3;
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ps->dpmx_nb_ps_hi = 0x0;
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if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
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if (pi->sys_info.nb_dpm_enable) {
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force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
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pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
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pi->disable_nb_ps3_in_battery;
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@ -2204,6 +2268,15 @@ static void kv_enable_new_levels(struct radeon_device *rdev)
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}
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}
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static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
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{
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u32 new_mask = (1 << level);
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return kv_send_msg_to_smc_with_parameter(rdev,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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new_mask);
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}
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static int kv_set_enabled_levels(struct radeon_device *rdev)
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{
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struct kv_power_info *pi = kv_get_pi(rdev);
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