KVM: arm64: Provide I-cache invalidation by virtual address at EL2
In preparation for handling cache maintenance of guest pages from within the pKVM hypervisor at EL2, introduce an EL2 copy of icache_inval_pou() which will later be plumbed into the stage-2 page-table cache maintenance callbacks, ensuring that the initial contents of pages mapped as executable into the guest stage-2 page-table is visible to the instruction fetcher. Tested-by: Vincent Donnefort <vdonnefort@google.com> Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221110190259.26861-17-will@kernel.org
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@ -123,4 +123,5 @@ extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val);
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extern unsigned long kvm_nvhe_sym(__icache_flags);
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#endif /* __ARM64_KVM_HYP_H__ */
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@ -71,9 +71,6 @@ KVM_NVHE_ALIAS(nvhe_hyp_panic_handler);
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/* Vectors installed by hyp-init on reset HVC. */
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KVM_NVHE_ALIAS(__hyp_stub_vectors);
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/* Kernel symbol used by icache_is_vpipt(). */
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KVM_NVHE_ALIAS(__icache_flags);
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/* VMID bits set by the KVM VMID allocator */
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KVM_NVHE_ALIAS(kvm_arm_vmid_bits);
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@ -1894,6 +1894,7 @@ static void kvm_hyp_init_symbols(void)
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kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
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kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val) = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);
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kvm_nvhe_sym(__icache_flags) = __icache_flags;
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}
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static int kvm_hyp_init_protection(u32 hyp_va_bits)
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@ -12,3 +12,14 @@ SYM_FUNC_START(__pi_dcache_clean_inval_poc)
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ret
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SYM_FUNC_END(__pi_dcache_clean_inval_poc)
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SYM_FUNC_ALIAS(dcache_clean_inval_poc, __pi_dcache_clean_inval_poc)
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SYM_FUNC_START(__pi_icache_inval_pou)
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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ret
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_icache_inval_pou)
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SYM_FUNC_ALIAS(icache_inval_pou, __pi_icache_inval_pou)
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@ -12,6 +12,9 @@
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#include <nvhe/pkvm.h>
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#include <nvhe/trap_handler.h>
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/* Used by icache_is_vpipt(). */
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unsigned long __icache_flags;
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/*
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* Set trap register values based on features in ID_AA64PFR0.
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*/
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