The i.MX device tree updates for 3.17:
- Add device tree sources and pin function header for i.MX6SX SoC
- Initial imx6sx-sdb board support with FEC, MMC, USB, PMIC, Audio
and GPIO key enabled
- New board support: mbimxsd25 and mbimxsd27 from Eukrea, aristainetos
imx6dl boards, Rex Pro and Basic, Ka-Ro TX6
- Restructure imx6qdl-wandboard.dtsi for new rev C1 board
- Split M28EVK and M53EVK into SoM and EVK parts
- A few correction around SDMA, SSI and SATA device nodes
- Add eSATA support for Cubox-i board
- Updates on edmqmx6 to enable PCIe, I2C and CAN
- Use DT macro for clock ID for imx27 and imx6qdl
- Add FlexCAN support for VF610 SoC
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Merge tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Merge "ARM: imx: device tree updates for 3.17" from Shawn Guo:
The i.MX device tree updates for 3.17:
- Add device tree sources and pin function header for i.MX6SX SoC
- Initial imx6sx-sdb board support with FEC, MMC, USB, PMIC, Audio
and GPIO key enabled
- New board support: mbimxsd25 and mbimxsd27 from Eukrea, aristainetos
imx6dl boards, Rex Pro and Basic, Ka-Ro TX6
- Restructure imx6qdl-wandboard.dtsi for new rev C1 board
- Split M28EVK and M53EVK into SoM and EVK parts
- A few correction around SDMA, SSI and SATA device nodes
- Add eSATA support for Cubox-i board
- Updates on edmqmx6 to enable PCIe, I2C and CAN
- Use DT macro for clock ID for imx27 and imx6qdl
- Add FlexCAN support for VF610 SoC
* tag 'imx-dt-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (125 commits)
ARM: dts: vf610: add FlexCAN node
ARM: dts: add initial Rex Basic board support
ARM: dts: add initial Rex Pro board support
ARM: dts: mx5: Split M53EVK into SoM and EVK parts
ARM: dts: imx6: RIoTboard explicitly define pad settings
ARM: dts: vf610: fix length of eshdc1 register property
ARM: dts: Restructure imx6qdl-wandboard.dtsi for new rev C1 board.
ARM: dts: imx53: correct clock-names of SATA node
ARM: imx6: Align ssi nodes between mx6 variants
ARM: i.MX27 clk: dts: Use clock defines in DTS files
ARM: dts: imx: correct sdma compatbile for imx6sl and imx6sx
ARM: dts: imx6sx-sdb: Add audio support
ARM: dts: imx6sx: Pass the fsl,fifo-depth property
ARM: dts: imx6sx: Fix sdma node
ARM: dts: imx6: edmqmx6: Add can bus
ARM: dts: imx6: edmqmx6: Add two other i2c buses
ARM: dts: imx6: edmqmx6: Add PCIe support
ARM: dts: imx25-pdk: Add USB OTG support
ARM: dts: i.MX53: add aipstz nodes
ARM: dts: mxs: Split M28EVK into SoM and EVK parts
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
1409f3fd5b
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|
@ -0,0 +1,26 @@
|
|||
* Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx1-ccm".
|
||||
- reg: Address and length of the register set.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@0021b000 {
|
||||
#clock-cells = <1>;
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||||
compatible = "fsl,imx1-ccm";
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||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm: pwm@00208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
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||||
};
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||||
|
|
@ -0,0 +1,28 @@
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* Clock bindings for Freescale i.MX21
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx21-ccm".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts : Should contain CCM interrupt.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
Examples:
|
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clks: ccm@10027000{
|
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compatible = "fsl,imx21-ccm";
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reg = <0x10027000 0x800>;
|
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#clock-cells = <1>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx21-uart";
|
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reg = <0x1000a000 0x1000>;
|
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interrupts = <20>;
|
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clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
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<&clks IMX21_CLK_PER1>;
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clock-names = "ipg", "per";
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status = "disabled";
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||||
};
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|
@ -7,117 +7,22 @@ Required properties:
|
|||
- #clock-cells: Should be <1>
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|
||||
The clock consumer should specify the desired clock by having the clock
|
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ID in its "clocks" phandle cell. The following is a full list of i.MX27
|
||||
clocks and IDs.
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|
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Clock ID
|
||||
-----------------------
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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mpll_main2 5
|
||||
ahb 6
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ipg 7
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nfc_div 8
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per1_div 9
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per2_div 10
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per3_div 11
|
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per4_div 12
|
||||
vpu_sel 13
|
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vpu_div 14
|
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usb_div 15
|
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cpu_sel 16
|
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clko_sel 17
|
||||
cpu_div 18
|
||||
clko_div 19
|
||||
ssi1_sel 20
|
||||
ssi2_sel 21
|
||||
ssi1_div 22
|
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ssi2_div 23
|
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clko_en 24
|
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ssi2_ipg_gate 25
|
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ssi1_ipg_gate 26
|
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slcdc_ipg_gate 27
|
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sdhc3_ipg_gate 28
|
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sdhc2_ipg_gate 29
|
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sdhc1_ipg_gate 30
|
||||
scc_ipg_gate 31
|
||||
sahara_ipg_gate 32
|
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rtc_ipg_gate 33
|
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pwm_ipg_gate 34
|
||||
owire_ipg_gate 35
|
||||
lcdc_ipg_gate 36
|
||||
kpp_ipg_gate 37
|
||||
iim_ipg_gate 38
|
||||
i2c2_ipg_gate 39
|
||||
i2c1_ipg_gate 40
|
||||
gpt6_ipg_gate 41
|
||||
gpt5_ipg_gate 42
|
||||
gpt4_ipg_gate 43
|
||||
gpt3_ipg_gate 44
|
||||
gpt2_ipg_gate 45
|
||||
gpt1_ipg_gate 46
|
||||
gpio_ipg_gate 47
|
||||
fec_ipg_gate 48
|
||||
emma_ipg_gate 49
|
||||
dma_ipg_gate 50
|
||||
cspi3_ipg_gate 51
|
||||
cspi2_ipg_gate 52
|
||||
cspi1_ipg_gate 53
|
||||
nfc_baud_gate 54
|
||||
ssi2_baud_gate 55
|
||||
ssi1_baud_gate 56
|
||||
vpu_baud_gate 57
|
||||
per4_gate 58
|
||||
per3_gate 59
|
||||
per2_gate 60
|
||||
per1_gate 61
|
||||
usb_ahb_gate 62
|
||||
slcdc_ahb_gate 63
|
||||
sahara_ahb_gate 64
|
||||
lcdc_ahb_gate 65
|
||||
vpu_ahb_gate 66
|
||||
fec_ahb_gate 67
|
||||
emma_ahb_gate 68
|
||||
emi_ahb_gate 69
|
||||
dma_ahb_gate 70
|
||||
csi_ahb_gate 71
|
||||
brom_ahb_gate 72
|
||||
ata_ahb_gate 73
|
||||
wdog_ipg_gate 74
|
||||
usb_ipg_gate 75
|
||||
uart6_ipg_gate 76
|
||||
uart5_ipg_gate 77
|
||||
uart4_ipg_gate 78
|
||||
uart3_ipg_gate 79
|
||||
uart2_ipg_gate 80
|
||||
uart1_ipg_gate 81
|
||||
ckih_div1p5 82
|
||||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
mshc_div 87
|
||||
rtic_ipg_gate 88
|
||||
mshc_ipg_gate 89
|
||||
rtic_ahb_gate 90
|
||||
mshc_baud_gate 91
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,223 +7,13 @@ Required properties:
|
|||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
usbphy1_gate 191
|
||||
usbphy2_gate 192
|
||||
pll4_post_div 193
|
||||
pll5_post_div 194
|
||||
pll5_video_div 195
|
||||
eim_slow 196
|
||||
spdif 197
|
||||
cko2_sel 198
|
||||
cko2_podf 199
|
||||
cko2 200
|
||||
cko 201
|
||||
vdoa 202
|
||||
pll4_audio_div 203
|
||||
lvds1_sel 204
|
||||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
esai_ahb 208
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
for the full list of i.MX6 Quad and DualLite clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
|
|
@ -235,7 +25,7 @@ uart1: serial@02020000 {
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -157,10 +157,14 @@ dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
|
|||
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += \
|
||||
imx25-eukrea-mbimxsd25-baseboard.dtb \
|
||||
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
|
||||
imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
|
||||
imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
|
||||
imx25-karo-tx25.dtb \
|
||||
imx25-pdk.dtb \
|
||||
imx27-apf27.dtb \
|
||||
imx27-apf27dev.dtb \
|
||||
imx27-eukrea-mbimxsd27-baseboard.dtb \
|
||||
imx27-pdk.dtb \
|
||||
imx27-phytec-phycore-rdk.dtb \
|
||||
imx27-phytec-phycard-s-rdk.dtb \
|
||||
|
|
@ -182,6 +186,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx53-tx53-x03x.dtb \
|
||||
imx53-tx53-x13x.dtb \
|
||||
imx53-voipac-bsb.dtb \
|
||||
imx6dl-aristainetos_4.dtb \
|
||||
imx6dl-aristainetos_7.dtb \
|
||||
imx6dl-cubox-i.dtb \
|
||||
imx6dl-dfi-fs700-m60.dtb \
|
||||
imx6dl-gw51xx.dtb \
|
||||
|
|
@ -191,11 +197,16 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx6dl-hummingboard.dtb \
|
||||
imx6dl-nitrogen6x.dtb \
|
||||
imx6dl-phytec-pbab01.dtb \
|
||||
imx6dl-rex-basic.dtb \
|
||||
imx6dl-riotboard.dtb \
|
||||
imx6dl-sabreauto.dtb \
|
||||
imx6dl-sabrelite.dtb \
|
||||
imx6dl-sabresd.dtb \
|
||||
imx6dl-tx6dl-comtft.dtb \
|
||||
imx6dl-tx6u-801x.dtb \
|
||||
imx6dl-tx6u-811x.dtb \
|
||||
imx6dl-wandboard.dtb \
|
||||
imx6dl-wandboard-revb1.dtb \
|
||||
imx6q-arm2.dtb \
|
||||
imx6q-cm-fx6.dtb \
|
||||
imx6q-cubox-i.dtb \
|
||||
|
|
@ -209,13 +220,21 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx6q-gw54xx.dtb \
|
||||
imx6q-nitrogen6x.dtb \
|
||||
imx6q-phytec-pbab01.dtb \
|
||||
imx6q-rex-pro.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb \
|
||||
imx6q-sbc6x.dtb \
|
||||
imx6q-udoo.dtb \
|
||||
imx6q-wandboard.dtb \
|
||||
imx6q-wandboard-revb1.dtb \
|
||||
imx6q-tx6q-1010.dtb \
|
||||
imx6q-tx6q-1010-comtft.dtb \
|
||||
imx6q-tx6q-1020.dtb \
|
||||
imx6q-tx6q-1020-comtft.dtb \
|
||||
imx6q-tx6q-1110.dtb \
|
||||
imx6sl-evk.dtb \
|
||||
imx6sx-sdb.dtb \
|
||||
vf610-colibri.dtb \
|
||||
vf610-cosmic.dtb \
|
||||
vf610-twr.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
|
||||
|
||||
/ {
|
||||
model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
|
||||
compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
|
||||
|
||||
cmo_qvga: display {
|
||||
model = "CMO-QVGA";
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xcad08b80>;
|
||||
bus-width = <18>;
|
||||
native-mode = <&qvga_timings>;
|
||||
display-timings {
|
||||
qvga_timings: 320x240 {
|
||||
clock-frequency = <6500000>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <30>;
|
||||
hfront-porch = <38>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <3>;
|
||||
hsync-len = <15>;
|
||||
vsync-len = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_lcd_3v3: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
|
||||
regulator-name = "lcd-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
|
||||
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
|
||||
fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
display = <&cmo_qvga>;
|
||||
fsl,lpccr = <0x00a903ff>;
|
||||
lcd-supply = <®_lcd_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
|
||||
|
||||
/ {
|
||||
model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
|
||||
compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
|
||||
|
||||
dvi_svga: display {
|
||||
model = "DVI-SVGA";
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xfa208b80>;
|
||||
bus-width = <18>;
|
||||
native-mode = <&dvi_svga_timings>;
|
||||
display-timings {
|
||||
dvi_svga_timings: 800x600 {
|
||||
clock-frequency = <40000000>;
|
||||
hactive = <800>;
|
||||
vactive = <600>;
|
||||
hback-porch = <75>;
|
||||
hfront-porch = <75>;
|
||||
vback-porch = <7>;
|
||||
vfront-porch = <75>;
|
||||
hsync-len = <7>;
|
||||
vsync-len = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
display = <&dvi_svga>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "imx25-eukrea-mbimxsd25-baseboard.dts"
|
||||
|
||||
/ {
|
||||
model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
|
||||
compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
|
||||
|
||||
dvi_vga: display {
|
||||
model = "DVI-VGA";
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xfa208b80>;
|
||||
bus-width = <18>;
|
||||
native-mode = <&dvi_vga_timings>;
|
||||
display-timings {
|
||||
dvi_vga_timings: 640x480 {
|
||||
clock-frequency = <31250000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <100>;
|
||||
hfront-porch = <100>;
|
||||
vback-porch = <7>;
|
||||
vfront-porch = <100>;
|
||||
hsync-len = <7>;
|
||||
vsync-len = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
display = <&dvi_vga>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -155,7 +155,6 @@
|
|||
|
||||
&ssi1 {
|
||||
codec-handle = <&tlv320aic23>;
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -233,7 +233,6 @@
|
|||
|
||||
&ssi1 {
|
||||
codec-handle = <&codec>;
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -249,3 +248,10 @@
|
|||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
phy_type = "utmi";
|
||||
dr_mode = "otg";
|
||||
external-vbus-divider;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -312,7 +312,7 @@
|
|||
gpt4: timer@53f84000 {
|
||||
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
clocks = <&clks 9>, <&clks 45>;
|
||||
clocks = <&clks 95>, <&clks 47>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <1>;
|
||||
};
|
||||
|
|
@ -320,7 +320,7 @@
|
|||
gpt3: timer@53f88000 {
|
||||
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53f88000 0x4000>;
|
||||
clocks = <&clks 9>, <&clks 47>;
|
||||
clocks = <&clks 94>, <&clks 47>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <29>;
|
||||
};
|
||||
|
|
@ -328,7 +328,7 @@
|
|||
gpt2: timer@53f8c000 {
|
||||
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53f8c000 0x4000>;
|
||||
clocks = <&clks 9>, <&clks 47>;
|
||||
clocks = <&clks 93>, <&clks 47>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <53>;
|
||||
};
|
||||
|
|
@ -336,7 +336,7 @@
|
|||
gpt1: timer@53f90000 {
|
||||
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53f90000 0x4000>;
|
||||
clocks = <&clks 9>, <&clks 47>;
|
||||
clocks = <&clks 92>, <&clks 47>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <54>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Eukrea CPUIMX27";
|
||||
compatible = "eukrea,cpuimx27", "fsl,imx27";
|
||||
|
||||
memory {
|
||||
reg = <0xa0000000 0x04000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
clk14745600: clock@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <14745600>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nfc>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&owire {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_owire>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhc2>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh2>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
status = "okay";
|
||||
|
||||
nor: nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <2>;
|
||||
linux,mtd-name = "physmap-flash.0";
|
||||
fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
|
||||
};
|
||||
|
||||
uart8250@3,200000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart8250_1>;
|
||||
compatible = "ns8250";
|
||||
clocks = <&clk14745600>;
|
||||
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
|
||||
interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <3 0x200000 0x1000>;
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <1>;
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
uart8250@3,400000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart8250_2>;
|
||||
compatible = "ns8250";
|
||||
clocks = <&clk14745600>;
|
||||
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
|
||||
interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <3 0x400000 0x1000>;
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <1>;
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
uart8250@3,800000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart8250_3>;
|
||||
compatible = "ns8250";
|
||||
clocks = <&clk14745600>;
|
||||
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
|
||||
interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <3 0x800000 0x1000>;
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <1>;
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
uart8250@3,1000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart8250_4>;
|
||||
compatible = "ns8250";
|
||||
clocks = <&clk14745600>;
|
||||
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
|
||||
interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <3 0x1000000 0x1000>;
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <1>;
|
||||
no-loopback-test;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx27-eukrea-cpuimx27 {
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
|
||||
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
|
||||
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
|
||||
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
|
||||
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
|
||||
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
|
||||
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
|
||||
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
|
||||
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
|
||||
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
|
||||
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
|
||||
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
|
||||
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
|
||||
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
|
||||
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
|
||||
MX27_PAD_ATA_DATA13__FEC_COL 0x0
|
||||
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
|
||||
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_I2C_DATA__I2C_DATA 0x0
|
||||
MX27_PAD_I2C_CLK__I2C_CLK 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nfc: nfcgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_NFRB__NFRB 0x0
|
||||
MX27_PAD_NFCLE__NFCLE 0x0
|
||||
MX27_PAD_NFWP_B__NFWP_B 0x0
|
||||
MX27_PAD_NFCE_B__NFCE_B 0x0
|
||||
MX27_PAD_NFALE__NFALE 0x0
|
||||
MX27_PAD_NFRE_B__NFRE_B 0x0
|
||||
MX27_PAD_NFWE_B__NFWE_B 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_owire: owiregrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_RTCK__OWIRE 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sdhc2: sdhc2grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_SD2_CLK__SD2_CLK 0x0
|
||||
MX27_PAD_SD2_CMD__SD2_CMD 0x0
|
||||
MX27_PAD_SD2_D0__SD2_D0 0x0
|
||||
MX27_PAD_SD2_D1__SD2_D1 0x0
|
||||
MX27_PAD_SD2_D2__SD2_D2 0x0
|
||||
MX27_PAD_SD2_D3__SD2_D3 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
|
||||
MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
|
||||
MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
|
||||
MX27_PAD_USBH1_FS__UART4_RTS 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart8250_1: uart82501grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USB_PWR__GPIO2_23 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart8250_2: uart82502grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart8250_3: uart82503grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart8250_4: uart82504grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh2: usbh2grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
|
||||
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
|
||||
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
|
||||
MX27_PAD_USBH2_STP__USBH2_STP 0x0
|
||||
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
|
||||
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
|
||||
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
|
||||
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
|
||||
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
|
||||
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
|
||||
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
|
||||
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
|
||||
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
|
||||
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
|
||||
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
|
||||
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
|
||||
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
|
||||
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
|
||||
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
|
||||
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
|
||||
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
|
||||
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
|
||||
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx27-eukrea-cpuimx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Eukrea MBIMXSD27";
|
||||
compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27";
|
||||
|
||||
display0: CMO-QVGA {
|
||||
model = "CMO-QVGA";
|
||||
native-mode = <&timing0>;
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xfad08b80>;
|
||||
|
||||
display-timings {
|
||||
timing0: 320x240 {
|
||||
clock-frequency = <6500000>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <20>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <38>;
|
||||
vback-porch = <4>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "gpio-backlight";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpioleds>;
|
||||
|
||||
led1 {
|
||||
label = "system::live";
|
||||
gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "system::user";
|
||||
gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_lcd: regulator@0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdreg>;
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "LCD";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cspi1 {
|
||||
pinctrl-0 = <&pinctrl_cspi1>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
ads7846 {
|
||||
compatible = "ti,ads7846";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_touch>;
|
||||
reg = <0>;
|
||||
interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
|
||||
spi-cpol;
|
||||
spi-max-frequency = <1500000>;
|
||||
ti,keep-vref-on;
|
||||
};
|
||||
};
|
||||
|
||||
&fb {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_imxfb>;
|
||||
display = <&display0>;
|
||||
lcd-supply = <®_lcd>;
|
||||
fsl,dmacr = <0x00040060>;
|
||||
fsl,lscr1 = <0x00120300>;
|
||||
fsl,lpccr = <0x00a903ff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
codec: codec@1a {
|
||||
compatible = "ti,tlv320aic23";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_UP)
|
||||
MATRIX_KEY(0, 1, KEY_DOWN)
|
||||
MATRIX_KEY(1, 0, KEY_RIGHT)
|
||||
MATRIX_KEY(1, 1, KEY_LEFT)
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhc1>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssi1>;
|
||||
codec-handle = <&codec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
fsl,uart-has-rtscts;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
fsl,uart-has-rtscts;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
fsl,uart-has-rtscts;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx27-eukrea-cpuimx27-baseboard {
|
||||
pinctrl_cspi1: cspi1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
|
||||
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
|
||||
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
|
||||
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_PWMO__GPIO5_5 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpioleds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_PC_PWRON__GPIO6_16 0x0
|
||||
MX27_PAD_PC_CD2_B__GPIO6_19 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_imxfb: imxfbgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_LD0__LD0 0x0
|
||||
MX27_PAD_LD1__LD1 0x0
|
||||
MX27_PAD_LD2__LD2 0x0
|
||||
MX27_PAD_LD3__LD3 0x0
|
||||
MX27_PAD_LD4__LD4 0x0
|
||||
MX27_PAD_LD5__LD5 0x0
|
||||
MX27_PAD_LD6__LD6 0x0
|
||||
MX27_PAD_LD7__LD7 0x0
|
||||
MX27_PAD_LD8__LD8 0x0
|
||||
MX27_PAD_LD9__LD9 0x0
|
||||
MX27_PAD_LD10__LD10 0x0
|
||||
MX27_PAD_LD11__LD11 0x0
|
||||
MX27_PAD_LD12__LD12 0x0
|
||||
MX27_PAD_LD13__LD13 0x0
|
||||
MX27_PAD_LD14__LD14 0x0
|
||||
MX27_PAD_LD15__LD15 0x0
|
||||
MX27_PAD_LD16__LD16 0x0
|
||||
MX27_PAD_LD17__LD17 0x0
|
||||
MX27_PAD_CONTRAST__CONTRAST 0x0
|
||||
MX27_PAD_OE_ACD__OE_ACD 0x0
|
||||
MX27_PAD_HSYNC__HSYNC 0x0
|
||||
MX27_PAD_VSYNC__VSYNC 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdreg: lcdreggrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_CLS__GPIO1_25 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sdhc1: sdhc1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_SD1_CLK__SD1_CLK 0x0
|
||||
MX27_PAD_SD1_CMD__SD1_CMD 0x0
|
||||
MX27_PAD_SD1_D0__SD1_D0 0x0
|
||||
MX27_PAD_SD1_D1__SD1_D1 0x0
|
||||
MX27_PAD_SD1_D2__SD1_D2 0x0
|
||||
MX27_PAD_SD1_D3__SD1_D3 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ssi1: ssi1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_SSI4_CLK__SSI4_CLK 0x0
|
||||
MX27_PAD_SSI4_FS__SSI4_FS 0x0
|
||||
MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1
|
||||
MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_touch: touchgrp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_UART1_TXD__UART1_TXD 0x0
|
||||
MX27_PAD_UART1_RXD__UART1_RXD 0x0
|
||||
MX27_PAD_UART1_CTS__UART1_CTS 0x0
|
||||
MX27_PAD_UART1_RTS__UART1_RTS 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_UART2_TXD__UART2_TXD 0x0
|
||||
MX27_PAD_UART2_RXD__UART2_RXD 0x0
|
||||
MX27_PAD_UART2_CTS__UART2_CTS 0x0
|
||||
MX27_PAD_UART2_RTS__UART2_RTS 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_UART3_TXD__UART3_TXD 0x0
|
||||
MX27_PAD_UART3_RXD__UART3_RXD 0x0
|
||||
MX27_PAD_UART3_CTS__UART3_CTS 0x0
|
||||
MX27_PAD_UART3_RTS__UART3_RTS 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reg = <0>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX27_CLK_DUMMY>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@
|
|||
compatible = "usb-nop-xceiv";
|
||||
reg = <2>;
|
||||
vcc-supply = <®_5v0>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX27_CLK_DUMMY>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@
|
|||
compatible = "usb-nop-xceiv";
|
||||
reg = <0>;
|
||||
vcc-supply = <&sw3_reg>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX27_CLK_DUMMY>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
|
@ -310,7 +310,6 @@
|
|||
&ssi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ssi1>;
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,9 +11,11 @@
|
|||
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx27-pinfunc.h"
|
||||
|
||||
#include <dt-bindings/clock/imx27-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -68,7 +70,7 @@
|
|||
399000 1450000
|
||||
>;
|
||||
clock-latency = <62500>;
|
||||
clocks = <&clks 18>;
|
||||
clocks = <&clks IMX27_CLK_CPU_DIV>;
|
||||
voltage-tolerance = <5>;
|
||||
};
|
||||
};
|
||||
|
|
@ -91,7 +93,8 @@
|
|||
compatible = "fsl,imx27-dma";
|
||||
reg = <0x10001000 0x1000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks 50>, <&clks 70>;
|
||||
clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
|
||||
<&clks IMX27_CLK_DMA_AHB_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <16>;
|
||||
|
|
@ -101,14 +104,15 @@
|
|||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clks 74>;
|
||||
clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
|
||||
};
|
||||
|
||||
gpt1: timer@10003000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10003000 0x1000>;
|
||||
interrupts = <26>;
|
||||
clocks = <&clks 46>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -116,7 +120,8 @@
|
|||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10004000 0x1000>;
|
||||
interrupts = <25>;
|
||||
clocks = <&clks 45>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -124,7 +129,8 @@
|
|||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10005000 0x1000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks 44>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -133,7 +139,8 @@
|
|||
compatible = "fsl,imx27-pwm";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupts = <23>;
|
||||
clocks = <&clks 34>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -141,14 +148,14 @@
|
|||
compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x10008000 0x1000>;
|
||||
interrupts = <21>;
|
||||
clocks = <&clks 37>;
|
||||
clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
owire: owire@10009000 {
|
||||
compatible = "fsl,imx27-owire", "fsl,imx21-owire";
|
||||
reg = <0x10009000 0x1000>;
|
||||
clocks = <&clks 35>;
|
||||
clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -156,7 +163,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -165,7 +173,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&clks 80>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -174,7 +183,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks 79>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -183,7 +193,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks 78>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -194,7 +205,8 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000e000 0x1000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 53>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -205,7 +217,8 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
interrupts = <15>;
|
||||
clocks = <&clks 52>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -215,7 +228,7 @@
|
|||
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x10010000 0x1000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks 26>;
|
||||
clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
|
||||
dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
|
||||
dma-names = "rx0", "tx0", "rx1", "tx1";
|
||||
fsl,fifo-depth = <8>;
|
||||
|
|
@ -227,7 +240,7 @@
|
|||
compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x10011000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks 25>;
|
||||
clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
|
||||
dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
|
||||
dma-names = "rx0", "tx0", "rx1", "tx1";
|
||||
fsl,fifo-depth = <8>;
|
||||
|
|
@ -240,7 +253,7 @@
|
|||
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x10012000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clks 40>;
|
||||
clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -248,7 +261,8 @@
|
|||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x10013000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&clks 30>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 7>;
|
||||
dma-names = "rx-tx";
|
||||
|
|
@ -259,7 +273,8 @@
|
|||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x10014000 0x1000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clks 29>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 6>;
|
||||
dma-names = "rx-tx";
|
||||
|
|
@ -276,6 +291,7 @@
|
|||
gpio1: gpio@10015000 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015000 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -286,6 +302,7 @@
|
|||
gpio2: gpio@10015100 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015100 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -296,6 +313,7 @@
|
|||
gpio3: gpio@10015200 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015200 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -306,6 +324,7 @@
|
|||
gpio4: gpio@10015300 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015300 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -316,6 +335,7 @@
|
|||
gpio5: gpio@10015400 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015400 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -326,6 +346,7 @@
|
|||
gpio6: gpio@10015500 {
|
||||
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
|
||||
reg = <0x10015500 0x100>;
|
||||
clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
|
||||
interrupts = <8>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -337,7 +358,7 @@
|
|||
audmux: audmux@10016000 {
|
||||
compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
|
||||
reg = <0x10016000 0x1000>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX27_CLK_DUMMY>;
|
||||
clock-names = "audmux";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -348,7 +369,8 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 51>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -357,7 +379,8 @@
|
|||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10019000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 43>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -365,7 +388,8 @@
|
|||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x1001a000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks 42>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -373,7 +397,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1001b000 0x1000>;
|
||||
interrupts = <49>;
|
||||
clocks = <&clks 77>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -382,7 +407,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1001c000 0x1000>;
|
||||
interrupts = <48>;
|
||||
clocks = <&clks 78>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -393,7 +419,7 @@
|
|||
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x1001d000 0x1000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks 39>;
|
||||
clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -401,7 +427,8 @@
|
|||
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
||||
reg = <0x1001e000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 28>, <&clks 60>;
|
||||
clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&dma 36>;
|
||||
dma-names = "rx-tx";
|
||||
|
|
@ -412,7 +439,8 @@
|
|||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x1001f000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks 41>, <&clks 61>;
|
||||
clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
};
|
||||
|
|
@ -428,7 +456,9 @@
|
|||
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
|
||||
interrupts = <61>;
|
||||
reg = <0x10021000 0x1000>;
|
||||
clocks = <&clks 36>, <&clks 65>, <&clks 59>;
|
||||
clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
|
||||
<&clks IMX27_CLK_LCDC_AHB_GATE>,
|
||||
<&clks IMX27_CLK_PER3_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -437,7 +467,8 @@
|
|||
compatible = "fsl,imx27-vpu";
|
||||
reg = <0x10023000 0x0200>;
|
||||
interrupts = <53>;
|
||||
clocks = <&clks 57>, <&clks 66>;
|
||||
clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
|
||||
<&clks IMX27_CLK_VPU_AHB_GATE>;
|
||||
clock-names = "per", "ahb";
|
||||
iram = <&iram>;
|
||||
};
|
||||
|
|
@ -446,7 +477,7 @@
|
|||
compatible = "fsl,imx27-usb";
|
||||
reg = <0x10024000 0x200>;
|
||||
interrupts = <56>;
|
||||
clocks = <&clks 75>;
|
||||
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -455,7 +486,7 @@
|
|||
compatible = "fsl,imx27-usb";
|
||||
reg = <0x10024200 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&clks 75>;
|
||||
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -464,7 +495,7 @@
|
|||
compatible = "fsl,imx27-usb";
|
||||
reg = <0x10024400 0x200>;
|
||||
interrupts = <55>;
|
||||
clocks = <&clks 75>;
|
||||
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -473,14 +504,15 @@
|
|||
#index-cells = <1>;
|
||||
compatible = "fsl,imx27-usbmisc";
|
||||
reg = <0x10024600 0x200>;
|
||||
clocks = <&clks 62>;
|
||||
clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
|
||||
};
|
||||
|
||||
sahara2: sahara@10025000 {
|
||||
compatible = "fsl,imx27-sahara";
|
||||
reg = <0x10025000 0x1000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks 32>, <&clks 64>;
|
||||
clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
|
||||
<&clks IMX27_CLK_SAHARA_AHB_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
};
|
||||
|
||||
|
|
@ -494,14 +526,15 @@
|
|||
compatible = "fsl,imx27-iim";
|
||||
reg = <0x10028000 0x1000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks 38>;
|
||||
clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
|
||||
};
|
||||
|
||||
fec: ethernet@1002b000 {
|
||||
compatible = "fsl,imx27-fec";
|
||||
reg = <0x1002b000 0x4000>;
|
||||
interrupts = <50>;
|
||||
clocks = <&clks 48>, <&clks 67>;
|
||||
clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
|
||||
<&clks IMX27_CLK_FEC_AHB_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -513,7 +546,7 @@
|
|||
compatible = "fsl,imx27-nand";
|
||||
reg = <0xd8000000 0x1000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 54>;
|
||||
clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -522,7 +555,7 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "fsl,imx27-weim";
|
||||
reg = <0xd8002000 0x1000>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
|
||||
ranges = <
|
||||
0 0 0xc0000000 0x08000000
|
||||
1 0 0xc8000000 0x08000000
|
||||
|
|
|
|||
|
|
@ -53,6 +53,17 @@
|
|||
fsl,pull-up = <MXS_PULL_DISABLE>;
|
||||
};
|
||||
|
||||
mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31c3 /*
|
||||
MX28_PAD_PWM3__GPIO_3_28 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
|
|
@ -60,6 +71,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_4bit_pins_a
|
||||
&mmc0_cd_cfg &mmc0_sck_cfg>;
|
||||
vmmc-supply = <®_vddio_sd0>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -116,4 +128,14 @@
|
|||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
reg_vddio_sd0: vddio-sd0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc_pwr_cfa10036>;
|
||||
regulator-name = "vddio-sd0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 28 0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx28.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M28";
|
||||
compatible = "denx,m28", "fsl,imx28";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x08000000>;
|
||||
};
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
gpmi-nand@8000c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader";
|
||||
reg = <0x00000000 0x00300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "environment";
|
||||
reg = <0x00300000 0x00080000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "redundant-environment";
|
||||
reg = <0x00380000 0x00080000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "kernel";
|
||||
reg = <0x00400000 0x00400000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "filesystem";
|
||||
reg = <0x00800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -10,52 +10,14 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx28.dtsi"
|
||||
#include "imx28-m28.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M28EVK";
|
||||
compatible = "denx,m28evk", "fsl,imx28";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x08000000>;
|
||||
};
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
gpmi-nand@8000c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader";
|
||||
reg = <0x00000000 0x00300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "environment";
|
||||
reg = <0x00300000 0x00080000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "redundant-environment";
|
||||
reg = <0x00380000 0x00080000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "kernel";
|
||||
reg = <0x00400000 0x00400000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "filesystem";
|
||||
reg = <0x00800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
compatible = "fsl,imx28-mmc";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -175,10 +137,6 @@
|
|||
};
|
||||
|
||||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
|
|
@ -192,11 +150,6 @@
|
|||
reg = <0x51>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
|
|
@ -284,19 +237,6 @@
|
|||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vddio_sd0: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
|
|
|
|||
|
|
@ -133,7 +133,6 @@
|
|||
|
||||
&ssi1 {
|
||||
codec-handle = <&tlv320aic23>;
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -193,6 +193,14 @@
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpt: timer@53f90000 {
|
||||
compatible = "fsl,imx35-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53f90000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 9>, <&clks 50>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpio3: gpio@53fa4000 {
|
||||
compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x53fa4000 0x4000>;
|
||||
|
|
|
|||
|
|
@ -151,8 +151,10 @@
|
|||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -457,8 +459,10 @@
|
|||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -203,6 +203,7 @@
|
|||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,mc13xxx-uses-rtc;
|
||||
|
||||
regulators {
|
||||
sw1_reg: sw1 {
|
||||
|
|
@ -392,7 +393,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -255,7 +255,6 @@
|
|||
|
||||
&ssi2 {
|
||||
codec-handle = <&tlv320aic23>;
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -218,7 +218,6 @@
|
|||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -508,7 +507,6 @@
|
|||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -564,7 +562,6 @@
|
|||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M53";
|
||||
compatible = "denx,imx53-m53", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p2v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_backlight: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "lcd-supply";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
stmpe610@41 {
|
||||
compatible = "st,stmpe610";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x41>;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
interrupts = <6 0x0>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
reg = <0>;
|
||||
st,sample-time = <4>;
|
||||
st,mod-12b = <1>;
|
||||
st,ref-sel = <0>;
|
||||
st,adc-freq = <1>;
|
||||
st,ave-ctrl = <3>;
|
||||
st,touch-det-delay = <3>;
|
||||
st,settling = <4>;
|
||||
st,fraction-z = <7>;
|
||||
st,i-drive = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -10,17 +10,12 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx53.dtsi"
|
||||
#include "imx53-m53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "DENX M53EVK";
|
||||
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
display1: display@di1 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "bgr666";
|
||||
|
|
@ -81,25 +76,6 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p2v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P2V";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
||||
reg_backlight: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "lcd-supply";
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
|
|
@ -174,50 +150,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
stmpe610@41 {
|
||||
compatible = "st,stmpe610";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x41>;
|
||||
id = <0>;
|
||||
blocks = <0x5>;
|
||||
interrupts = <6 0x0>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
reg = <0>;
|
||||
st,sample-time = <4>;
|
||||
st,mod-12b = <1>;
|
||||
st,ref-sel = <0>;
|
||||
st,adc-freq = <1>;
|
||||
st,ave-ctrl = <3>;
|
||||
st,touch-det-delay = <3>;
|
||||
st,settling = <4>;
|
||||
st,fraction-z = <7>;
|
||||
st,i-drive = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t62";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
|
|
@ -229,11 +161,8 @@
|
|||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
pinctrl_hog: hoggrp {
|
||||
pinctrl_usb: usbgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x80000000
|
||||
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
|
||||
>;
|
||||
|
|
@ -302,13 +231,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
|
|
@ -353,26 +275,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_nand: nandgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
||||
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
||||
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
||||
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
||||
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
||||
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
||||
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
||||
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
||||
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
||||
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
||||
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
||||
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
||||
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
||||
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
||||
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
||||
|
|
@ -408,14 +310,6 @@
|
|||
remote-endpoint = <&display1_in>;
|
||||
};
|
||||
|
||||
&nfc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
|
|
@ -427,7 +321,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -450,6 +343,8 @@
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
phy_type = "utmi";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -225,7 +225,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -141,7 +141,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -502,7 +502,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
codec-handle = <&sgtl5000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -154,6 +154,5 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@
|
|||
clocks = <&clks IMX5_CLK_SATA_GATE>,
|
||||
<&clks IMX5_CLK_SATA_REF>,
|
||||
<&clks IMX5_CLK_AHB>;
|
||||
clock-names = "sata_gate", "sata_ref", "ahb";
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -231,7 +231,6 @@
|
|||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -260,6 +259,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
aipstz1: bridge@53f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x53f00000 0x60>;
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
|
||||
|
|
@ -572,6 +576,11 @@
|
|||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
aipstz2: bridge@63f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x63f00000 0x60>;
|
||||
};
|
||||
|
||||
iim: iim@63f98000 {
|
||||
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
||||
reg = <0x63f98000 0x4000>;
|
||||
|
|
@ -661,7 +670,6 @@
|
|||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -689,7 +697,6 @@
|
|||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* support fot the imx6 based aristainetos board
|
||||
*
|
||||
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-aristainetos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "aristainetos i.MX6 Dual Lite Board 4";
|
||||
compatible = "fsl,imx6dl";
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
480x800p60 {
|
||||
native-mode;
|
||||
clock-frequency = <30000000>;
|
||||
hactive = <480>;
|
||||
vactive = <800>;
|
||||
hfront-porch = <59>;
|
||||
hback-porch = <10>;
|
||||
hsync-len = <10>;
|
||||
vback-porch = <15>;
|
||||
vfront-porch = <15>;
|
||||
vsync-len = <15>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* support fot the imx6 based aristainetos board
|
||||
*
|
||||
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-aristainetos.dtsi"
|
||||
|
||||
/ {
|
||||
model = "aristainetos i.MX6 Dual Lite Board 7";
|
||||
compatible = "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
display0: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu_disp>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
800x480p60 {
|
||||
native-mode;
|
||||
clock-frequency = <33246000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <88>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <80>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <25>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 3000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
|
@ -14,6 +14,6 @@
|
|||
#include "imx6qdl-gw51xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite GW51XX";
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
|
||||
compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,6 @@
|
|||
#include "imx6qdl-gw52xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite GW52XX";
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
|
||||
compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,6 @@
|
|||
#include "imx6qdl-gw53xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite GW53XX";
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
|
||||
compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,6 @@
|
|||
#include "imx6qdl-gw54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 DualLite GW54XX";
|
||||
model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
|
||||
compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright 2014 FEDEVEL, Inc.
|
||||
*
|
||||
* Author: Robert Nelson <robertcnelson@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-rex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rex Basic i.MX6 Dual Lite Board";
|
||||
compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf016b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -254,7 +254,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -335,10 +334,10 @@
|
|||
imx6-riotboard {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
|
||||
>;
|
||||
};
|
||||
|
|
@ -376,7 +375,7 @@
|
|||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
|
|
@ -389,9 +388,9 @@
|
|||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
|
@ -426,8 +425,8 @@
|
|||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */
|
||||
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
|
||||
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -493,8 +492,8 @@
|
|||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
|
||||
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
|
||||
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -506,8 +505,8 @@
|
|||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -519,8 +518,8 @@
|
|||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -532,7 +531,7 @@
|
|||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6DL Module on CoMpact TFT";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&ET070001DM6>;
|
||||
|
||||
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®_can_xcvr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-801x Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-811x Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_lcd0_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 0>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
polytouch2: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6dl-tx6u-811x {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled"; /* pad conflict with backlight1 PWM */
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing0>;
|
||||
lvds_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "disabled";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing1>;
|
||||
lvds_timing1: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-wandboard-revb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
#include "imx6qdl-wandboard-revc1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
|
|
|
|||
|
|
@ -35,8 +35,11 @@
|
|||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
|
||||
<&clks 17>, <&clks 170>;
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
|
|
@ -56,7 +59,7 @@
|
|||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
clocks = <&clks 142>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@02000000 {
|
||||
|
|
@ -87,7 +90,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021f8000 0x4000>;
|
||||
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 116>;
|
||||
clocks = <&clks IMX6DL_CLK_I2C4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -104,9 +107,9 @@
|
|||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks 33>, <&clks 34>,
|
||||
<&clks 39>, <&clks 40>,
|
||||
<&clks 135>, <&clks 136>;
|
||||
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
|
|
|
|||
|
|
@ -13,4 +13,8 @@
|
|||
|
||||
&sata {
|
||||
status = "okay";
|
||||
fsl,transmit-level-mV = <1104>;
|
||||
fsl,transmit-boost-mdB = <0>;
|
||||
fsl,transmit-atten-16ths = <9>;
|
||||
fsl,no-spread-spectrum;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -95,6 +95,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi5>;
|
||||
|
|
@ -118,6 +124,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -274,6 +287,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
|
@ -286,6 +306,13 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi5: ecspi5rp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
|
||||
|
|
@ -316,6 +343,13 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
|
|
@ -323,6 +357,19 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pfuze: pfuze100grp1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
|
||||
|
|
@ -385,6 +432,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio4 8 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,6 @@
|
|||
#include "imx6qdl-gw51xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW51XX";
|
||||
model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX";
|
||||
compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "imx6qdl-gw52xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW52XX";
|
||||
model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
|
||||
compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "imx6qdl-gw53xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW53XX";
|
||||
model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
|
||||
compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -115,9 +115,9 @@
|
|||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-sabrelite-sgtl5000",
|
||||
compatible = "fsl,imx6q-ventana-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-sabrelite-sgtl5000";
|
||||
model = "sgtl5000-audio";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -504,7 +504,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "imx6qdl-gw54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW54XX";
|
||||
model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
|
||||
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright 2014 FEDEVEL, Inc.
|
||||
*
|
||||
* Author: Robert Nelson <robertcnelson@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-rex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rex Pro i.MX6 Quad Board";
|
||||
compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
flash: m25p80@0 {
|
||||
compatible = "sst,sst25vf032b";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&ET070001DM6>;
|
||||
|
||||
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®_can_xcvr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1010 Module";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&ET070001DM6>;
|
||||
|
||||
ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_3v3>;
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®_can_xcvr {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1020 Module";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &display;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
|
||||
power-supply = <®_3v3>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_disp0_1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <48>;
|
||||
hsync-len = <96>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <31>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <12>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETV570 {
|
||||
clock-frequency = <25200000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <114>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <16>;
|
||||
vback-porch = <32>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0350 {
|
||||
clock-frequency = <6413760>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <34>;
|
||||
hsync-len = <34>;
|
||||
hfront-porch = <20>;
|
||||
vback-porch = <15>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0430 {
|
||||
clock-frequency = <9009000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
hfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
vfront-porch = <2>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
ET0500 {
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ET0700 { /* same as ET0500 */
|
||||
clock-frequency = <33264000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <128>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
vfront-porch = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
ETQ570 {
|
||||
clock-frequency = <6596040>;
|
||||
hactive = <320>;
|
||||
vactive = <240>;
|
||||
hback-porch = <38>;
|
||||
hsync-len = <30>;
|
||||
hfront-porch = <30>;
|
||||
vback-porch = <16>;
|
||||
vsync-len = <3>;
|
||||
vfront-porch = <4>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ds1339 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
|
||||
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-tx6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6Q-1110 Module";
|
||||
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
display = &lvds0;
|
||||
lvds0 = &lvds0;
|
||||
lvds1 = &lvds1;
|
||||
};
|
||||
|
||||
backlight0: backlight0 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm2 0 500000 0>;
|
||||
power-supply = <®_lcd0_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
|
||||
backlight1: backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 500000 0>;
|
||||
power-supply = <®_lcd1_pwr>;
|
||||
/*
|
||||
* a poor man's way to create a 1:1 relationship between
|
||||
* the PWM value and the actual duty cycle
|
||||
*/
|
||||
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
||||
10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29
|
||||
30 31 32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47 48 49
|
||||
50 51 52 53 54 55 56 57 58 59
|
||||
60 61 62 63 64 65 66 67 68 69
|
||||
70 71 72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87 88 89
|
||||
90 91 92 93 94 95 96 97 98 99
|
||||
100>;
|
||||
default-brightness-level = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
polytouch1: eeti@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_eeti>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6q-tx6q-1110 {
|
||||
pinctrl_eeti: eetigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
status = "disabled"; /* pad conflict with backlight1 PWM */
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing0>;
|
||||
lvds_timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "disabled";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lvds_timing1>;
|
||||
lvds_timing1: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -23,6 +23,23 @@
|
|||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usb_h1_vbus: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
|
||||
gpio = <&gpio7 12 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
|
|
@ -81,6 +98,13 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh: usbhgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
|
|
@ -104,6 +128,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh>;
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
clocks = <&clks 201>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-wandboard-revb1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Quad Board";
|
||||
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
#include "imx6qdl-wandboard-revc1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Quad Board";
|
||||
|
|
|
|||
|
|
@ -43,8 +43,11 @@
|
|||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
|
||||
<&clks 17>, <&clks 170>;
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
|
|
@ -78,7 +81,7 @@
|
|||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x40000>;
|
||||
clocks = <&clks 142>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
|
|
@ -89,7 +92,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 116>, <&clks 116>;
|
||||
clocks = <&clks IMX6Q_CLK_ECSPI5>,
|
||||
<&clks IMX6Q_CLK_ECSPI5>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -140,7 +144,9 @@
|
|||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 154>, <&clks 187>, <&clks 105>;
|
||||
clocks = <&clks IMX6QDL_CLK_SATA>,
|
||||
<&clks IMX6QDL_CLK_SATA_REF_100M>,
|
||||
<&clks IMX6QDL_CLK_AHB>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -152,10 +158,20 @@
|
|||
reg = <0x02800000 0x400000>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPU2>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI1>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 4>;
|
||||
|
||||
ipu2_csi0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu2_csi1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
ipu2_di0: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -230,9 +246,10 @@
|
|||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks 33>, <&clks 34>,
|
||||
<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
|
||||
<&clks 135>, <&clks 136>;
|
||||
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
|
||||
"di0", "di1";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,418 @@
|
|||
/*
|
||||
* support fot the imx6 based aristainetos board
|
||||
*
|
||||
* Copyright (C) 2014 Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_2p5v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
tmp103: tmp103@71 {
|
||||
compatible = "ti,tmp103";
|
||||
reg = <0x71>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,m41t00";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi4 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 20 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi4>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
cd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
cd-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
|
||||
|
||||
imx6qdl-aristainetos {
|
||||
pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
|
||||
};
|
||||
|
||||
pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi4: ecspi4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1
|
||||
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
|
||||
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio: gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu_disp: ipudisp1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
|
||||
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -121,9 +121,9 @@
|
|||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-sabrelite-sgtl5000",
|
||||
compatible = "fsl,imx6q-ventana-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-sabrelite-sgtl5000";
|
||||
model = "sgtl5000-audio";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -489,7 +489,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -124,9 +124,9 @@
|
|||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-sabrelite-sgtl5000",
|
||||
compatible = "fsl,imx6q-ventana-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-sabrelite-sgtl5000";
|
||||
model = "sgtl5000-audio";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -533,7 +533,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -114,9 +114,9 @@
|
|||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-sabrelite-sgtl5000",
|
||||
compatible = "fsl,imx6q-ventana-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-sabrelite-sgtl5000";
|
||||
model = "sgtl5000-audio";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -555,12 +555,10 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -381,7 +381,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -301,6 +301,7 @@
|
|||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
|
||||
phy-supply = <&vdd_eth_io_reg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,357 @@
|
|||
/*
|
||||
* Copyright 2014 FEDEVEL, Inc.
|
||||
*
|
||||
* Author: Robert Nelson <robertcnelson@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3p3v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led>;
|
||||
|
||||
led0: usr {
|
||||
label = "usr";
|
||||
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6-rex-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6-rex-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_3p3v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "at,24c02";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-rex {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
/* SGTL5000 sys_mclk */
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||||
/* CS */
|
||||
MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
|
||||
/* CS */
|
||||
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
/* Phy reset */
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
/* user led */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1: usbh1grp {
|
||||
fsl,pins = <
|
||||
/* power enable, high active */
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
|
||||
/* power enable, high active */
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
/* CD */
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
/* WP */
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
/* CD */
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
/* WP */
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -381,7 +381,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -340,6 +340,7 @@
|
|||
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -512,7 +513,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,696 @@
|
|||
/*
|
||||
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
can0 = &can2;
|
||||
can1 = &can1;
|
||||
ethernet0 = &fec;
|
||||
lcdif_23bit_pins_a = &pinctrl_disp0_1;
|
||||
lcdif_24bit_pins_a = &pinctrl_disp0_2;
|
||||
pwm0 = &pwm1;
|
||||
pwm1 = &pwm2;
|
||||
reg_can_xcvr = ®_can_xcvr;
|
||||
stk5led = &user_led;
|
||||
usbotg = &usbotg;
|
||||
sdhc0 = &usdhc1;
|
||||
sdhc1 = &usdhc2;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0>; /* will be filled by U-Boot */
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mclk: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user_led: user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_3v3_etn: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "3V3_ETN";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_etnphy_power>;
|
||||
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_2v5: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "2V5";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3v3: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_can_xcvr: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "CAN XCVR";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
|
||||
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-low;
|
||||
};
|
||||
|
||||
reg_lcd0_pwr: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "LCD0 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd0_pwr>;
|
||||
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_lcd1_pwr: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
regulator-name = "LCD1 POWER";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd1_pwr>;
|
||||
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbh1_vbus: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
regulator-name = "usbh1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh1_vbus>;
|
||||
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator@7 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <7>;
|
||||
regulator-name = "usbotg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_vbus>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "sgtl5000-audio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&sgtl5000>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
xceiver-supply = <®_can_xcvr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_can_xcvr>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <
|
||||
&gpio2 30 GPIO_ACTIVE_HIGH
|
||||
&gpio3 19 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
status = "okay";
|
||||
|
||||
spidev0: spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
|
||||
spidev1: spi@1 {
|
||||
compatible = "spidev";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
|
||||
phy-supply = <®_3v3_etn>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
||||
nand-on-flash-bbt;
|
||||
fsl,no-blockmark-swap;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
ds1339: rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
VDDA-supply = <®_2v5>;
|
||||
VDDIO-supply = <®_3v3>;
|
||||
clocks = <&mclk>;
|
||||
};
|
||||
|
||||
polytouch: edt-ft5x06@38 {
|
||||
compatible = "edt,edt-ft5x06";
|
||||
reg = <0x38>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_edt_ft5x06>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <15 0>;
|
||||
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,wakeup;
|
||||
};
|
||||
|
||||
touchscreen: tsc2007@48 {
|
||||
compatible = "ti,tsc2007";
|
||||
reg = <0x48>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc2007>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <26 0>;
|
||||
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
|
||||
ti,x-plate-ohms = <660>;
|
||||
linux,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
|
||||
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
|
||||
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
|
||||
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
|
||||
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_disp0_1: disp0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_disp0_2: disp0grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
|
||||
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
|
||||
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_edt_ft5x06: edt-ft5x06grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
|
||||
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
|
||||
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_etnphy_power: etnphy-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_kpp: kppgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
|
||||
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd0_pwr: lcd0-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd1_pwr: lcd1-pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc2007: tsc2007grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
|
||||
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp>;
|
||||
/* sample keymap */
|
||||
/* row/col 0,1 are mapped to KPP row/col 6,7 */
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
|
||||
MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
|
||||
MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
|
||||
MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
|
||||
MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
|
||||
MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
|
||||
MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
|
||||
MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
|
||||
MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
|
||||
MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
|
||||
MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
dr_mode = "peripheral";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
cd-gpios = <&gpio7 2 0>;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
cd-gpios = <&gpio7 3 0>;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-wandboard {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
|
||||
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
|
||||
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */
|
||||
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
|
||||
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
|
||||
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
|
||||
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-wandboard {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
|
||||
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
|
||||
MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */
|
||||
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */
|
||||
MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */
|
||||
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */
|
||||
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */
|
||||
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -91,22 +91,8 @@
|
|||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-wandboard {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
|
||||
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
|
||||
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
|
||||
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
|
|
@ -233,7 +219,6 @@
|
|||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -269,13 +254,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
|
@ -94,7 +95,7 @@
|
|||
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
clocks = <&clks 106>;
|
||||
clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
|
||||
};
|
||||
|
||||
gpmi: gpmi-nand@00112000 {
|
||||
|
|
@ -105,8 +106,11 @@
|
|||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bch";
|
||||
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
|
||||
<&clks 150>, <&clks 149>;
|
||||
clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
|
||||
<&clks IMX6QDL_CLK_GPMI_APB>,
|
||||
<&clks IMX6QDL_CLK_GPMI_BCH>,
|
||||
<&clks IMX6QDL_CLK_GPMI_BCH_APB>,
|
||||
<&clks IMX6QDL_CLK_PER1_BCH>;
|
||||
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
|
||||
"gpmi_bch_apb", "per1_bch";
|
||||
dmas = <&dma_apbh 0>;
|
||||
|
|
@ -118,7 +122,7 @@
|
|||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x00a00600 0x20>;
|
||||
interrupts = <1 13 0xf01>;
|
||||
clocks = <&clks 15>;
|
||||
clocks = <&clks IMX6QDL_CLK_TWD>;
|
||||
};
|
||||
|
||||
L2: l2-cache@00a02000 {
|
||||
|
|
@ -149,7 +153,9 @@
|
|||
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 144>, <&clks 206>, <&clks 189>;
|
||||
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
|
||||
<&clks IMX6QDL_CLK_LVDS1_GATE>,
|
||||
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
|
||||
clock-names = "pcie", "pcie_bus", "pcie_phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -180,11 +186,11 @@
|
|||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks 197>, <&clks 3>,
|
||||
<&clks 197>, <&clks 107>,
|
||||
<&clks 0>, <&clks 118>,
|
||||
<&clks 0>, <&clks 139>,
|
||||
<&clks 0>;
|
||||
clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
|
||||
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
|
|
@ -199,7 +205,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 112>, <&clks 112>;
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
|
||||
<&clks IMX6QDL_CLK_ECSPI1>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -212,7 +219,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 113>, <&clks 113>;
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
|
||||
<&clks IMX6QDL_CLK_ECSPI2>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -225,7 +233,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 114>, <&clks 114>;
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
|
||||
<&clks IMX6QDL_CLK_ECSPI3>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -238,7 +247,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 115>, <&clks 115>;
|
||||
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
|
||||
<&clks IMX6QDL_CLK_ECSPI4>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -249,7 +259,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
||||
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -263,46 +274,40 @@
|
|||
|
||||
ssi1: ssi@02028000 {
|
||||
compatible = "fsl,imx6q-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 178>;
|
||||
clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@0202c000 {
|
||||
compatible = "fsl,imx6q-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 179>;
|
||||
clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@02030000 {
|
||||
compatible = "fsl,imx6q-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 180>;
|
||||
clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -331,7 +336,8 @@
|
|||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 145>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPG>,
|
||||
<&clks IMX6QDL_CLK_PWM1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -340,7 +346,8 @@
|
|||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 146>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPG>,
|
||||
<&clks IMX6QDL_CLK_PWM2>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -349,7 +356,8 @@
|
|||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 147>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPG>,
|
||||
<&clks IMX6QDL_CLK_PWM3>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -358,7 +366,8 @@
|
|||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 148>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPG>,
|
||||
<&clks IMX6QDL_CLK_PWM4>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -366,7 +375,8 @@
|
|||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 108>, <&clks 109>;
|
||||
clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
|
||||
<&clks IMX6QDL_CLK_CAN1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -375,7 +385,8 @@
|
|||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 110>, <&clks 111>;
|
||||
clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
|
||||
<&clks IMX6QDL_CLK_CAN2_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -384,7 +395,8 @@
|
|||
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 119>, <&clks 120>;
|
||||
clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
|
||||
<&clks IMX6QDL_CLK_GPT_IPG_PER>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
|
|
@ -466,22 +478,25 @@
|
|||
};
|
||||
|
||||
kpp: kpp@020b8000 {
|
||||
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPG>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@020bc000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
wdog2: wdog@020c0000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -599,14 +614,14 @@
|
|||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
clocks = <&clks 172>;
|
||||
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@020c9000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 182>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
|
|
@ -614,7 +629,7 @@
|
|||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 183>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBPHY2>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
|
|
@ -727,7 +742,8 @@
|
|||
reg = <0x00120000 0x9000>;
|
||||
interrupts = <0 115 0x04>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 123>, <&clks 124>;
|
||||
clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
|
||||
<&clks IMX6QDL_CLK_HDMI_ISFR>;
|
||||
clock-names = "iahb", "isfr";
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -762,7 +778,8 @@
|
|||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clocks = <&clks IMX6QDL_CLK_SDMA>,
|
||||
<&clks IMX6QDL_CLK_SDMA>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
|
|
@ -790,7 +807,7 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
status = "disabled";
|
||||
|
|
@ -800,7 +817,7 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
|
|
@ -810,7 +827,7 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -819,7 +836,7 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184600 0x200>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -828,7 +845,7 @@
|
|||
#index-cells = <1>;
|
||||
compatible = "fsl,imx6q-usbmisc";
|
||||
reg = <0x02184800 0x200>;
|
||||
clocks = <&clks 162>;
|
||||
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
||||
};
|
||||
|
||||
fec: ethernet@02188000 {
|
||||
|
|
@ -837,7 +854,9 @@
|
|||
interrupts-extended =
|
||||
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
|
||||
clocks = <&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -853,7 +872,9 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
|
||||
clocks = <&clks IMX6QDL_CLK_USDHC1>,
|
||||
<&clks IMX6QDL_CLK_USDHC1>,
|
||||
<&clks IMX6QDL_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
|
|
@ -863,7 +884,9 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
|
||||
clocks = <&clks IMX6QDL_CLK_USDHC2>,
|
||||
<&clks IMX6QDL_CLK_USDHC2>,
|
||||
<&clks IMX6QDL_CLK_USDHC2>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
|
|
@ -873,7 +896,9 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
|
||||
clocks = <&clks IMX6QDL_CLK_USDHC3>,
|
||||
<&clks IMX6QDL_CLK_USDHC3>,
|
||||
<&clks IMX6QDL_CLK_USDHC3>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
|
|
@ -883,7 +908,9 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
|
||||
clocks = <&clks IMX6QDL_CLK_USDHC4>,
|
||||
<&clks IMX6QDL_CLK_USDHC4>,
|
||||
<&clks IMX6QDL_CLK_USDHC4>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
|
|
@ -895,7 +922,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 125>;
|
||||
clocks = <&clks IMX6QDL_CLK_I2C1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -905,7 +932,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 126>;
|
||||
clocks = <&clks IMX6QDL_CLK_I2C2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -915,7 +942,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 127>;
|
||||
clocks = <&clks IMX6QDL_CLK_I2C3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -936,7 +963,7 @@
|
|||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 196>;
|
||||
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
|
||||
};
|
||||
|
||||
ocotp: ocotp@021bc000 {
|
||||
|
|
@ -996,7 +1023,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
||||
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -1007,7 +1035,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
||||
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -1018,7 +1047,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
||||
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -1029,7 +1059,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
||||
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -1044,10 +1075,20 @@
|
|||
reg = <0x02400000 0x400000>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
|
||||
clocks = <&clks IMX6QDL_CLK_IPU1>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI1>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu1_csi0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu1_csi1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
ipu1_di0: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -116,8 +116,9 @@
|
|||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_fec>;
|
||||
pinctrl-1 = <&pinctrl_fec_sleep>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -300,6 +301,19 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_sleep: fecgrp-sleep {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
|
||||
MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
|
||||
MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
|
||||
MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
|
||||
MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
|
||||
MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
|
||||
MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
|
||||
MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
|
||||
|
|
@ -475,7 +489,6 @@
|
|||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -227,8 +227,7 @@
|
|||
|
||||
ssi1: ssi@02028000 {
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI1>;
|
||||
|
|
@ -241,8 +240,7 @@
|
|||
|
||||
ssi2: ssi@0202c000 {
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI2>;
|
||||
|
|
@ -255,8 +253,7 @@
|
|||
|
||||
ssi3: ssi@02030000 {
|
||||
compatible = "fsl,imx6sl-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
"fsl,imx51-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI3>;
|
||||
|
|
@ -403,6 +400,7 @@
|
|||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@020bc000 {
|
||||
|
|
@ -607,7 +605,7 @@
|
|||
};
|
||||
|
||||
sdma: sdma@020ec000 {
|
||||
compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
|
||||
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SL_CLK_SDMA>,
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,479 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "imx6sx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 SoloX SDB Board";
|
||||
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vcc_sd3: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vcc_sd3>;
|
||||
regulator-name = "VCC_SD3";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg2>;
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_psu_5v: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "PSU-5V0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
|
||||
model = "wm8962-audio";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Ext Spk", "SPKOUTL",
|
||||
"Ext Spk", "SPKOUTR",
|
||||
"AMIC", "MICBIAS",
|
||||
"IN3R", "AMIC";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
|
||||
codec: wm8962@1a {
|
||||
compatible = "wlf,wm8962";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks IMX6SX_CLK_AUDIO>;
|
||||
DCVDD-supply = <&vgen4_reg>;
|
||||
DBVDD-supply = <&vgen4_reg>;
|
||||
AVDD-supply = <&vgen4_reg>;
|
||||
CPVDD-supply = <&vgen4_reg>;
|
||||
MICVDD-supply = <&vgen3_reg>;
|
||||
PLLVDD-supply = <&vgen4_reg>;
|
||||
SPKVDD1-supply = <®_psu_5v>;
|
||||
SPKVDD2-supply = <®_psu_5v>;
|
||||
};
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 { /* for bluetooth */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_otg2_vbus>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakeup;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
|
||||
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakeup;
|
||||
vmmc-supply = <&vcc_sd3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
|
||||
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6x-sdb {
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
|
||||
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
|
||||
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
|
||||
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
|
||||
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
|
||||
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
|
||||
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
|
||||
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
|
||||
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
|
||||
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
|
||||
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
|
||||
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
|
||||
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
|
||||
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
|
||||
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
|
||||
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_vcc_sd3: vccsd3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
|
||||
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
|
||||
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
|
||||
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
|
||||
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg2: usbot2ggrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
|
||||
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
|
||||
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
|
||||
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
|
||||
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
|
||||
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
|
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
|
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
|
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
|
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
|
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
|
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
|
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
|
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
|
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
|
||||
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
|
||||
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
|
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
|
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
|
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
|
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
|
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
|
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
|
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
|
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
|
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
|
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
|
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
|
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
|
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
|
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
|
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
|
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
|
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
|
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
|
||||
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
|
||||
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
|
||||
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
|
||||
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
|
||||
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
|
||||
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
|
||||
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -14,6 +14,8 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
can0 = &can0;
|
||||
can1 = &can1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
|
|
@ -103,6 +105,16 @@
|
|||
<&clks VF610_CLK_DMAMUX1>;
|
||||
};
|
||||
|
||||
can0: flexcan@40020000 {
|
||||
compatible = "fsl,vf610-flexcan";
|
||||
reg = <0x40020000 0x4000>;
|
||||
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks VF610_CLK_FLEXCAN0>,
|
||||
<&clks VF610_CLK_FLEXCAN0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@40027000 {
|
||||
compatible = "fsl,vf610-lpuart";
|
||||
reg = <0x40027000 0x1000>;
|
||||
|
|
@ -362,7 +374,7 @@
|
|||
|
||||
esdhc1: esdhc@400b2000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x400b2000 0x4000>;
|
||||
reg = <0x400b2000 0x1000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
clocks = <&clks VF610_CLK_IPG_BUS>,
|
||||
<&clks VF610_CLK_PLATFORM_BUS>,
|
||||
|
|
@ -405,6 +417,17 @@
|
|||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: flexcan@400d4000 {
|
||||
compatible = "fsl,vf610-flexcan";
|
||||
reg = <0x400d4000 0x4000>;
|
||||
interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks VF610_CLK_FLEXCAN1>,
|
||||
<&clks VF610_CLK_FLEXCAN1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
|
|
@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
|
|||
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
|
||||
CONFIG_MACH_MX27_3DS=y
|
||||
CONFIG_MACH_IMX27_VISSTRIM_M10=y
|
||||
CONFIG_MACH_IMX27LITE=y
|
||||
CONFIG_MACH_PCA100=y
|
||||
CONFIG_MACH_MXT_TD60=y
|
||||
CONFIG_MACH_IMX27IPCAM=y
|
||||
CONFIG_MACH_IMX27_DT=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
|
|
@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
|
|||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_ETH=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_KERNEL_LZO=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=18
|
||||
|
|
@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y
|
|||
CONFIG_MACH_PCM043=y
|
||||
CONFIG_MACH_MX35_3DS=y
|
||||
CONFIG_MACH_VPR200=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
CONFIG_SOC_IMX50=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
CONFIG_SOC_IMX6SX=y
|
||||
CONFIG_SOC_VF610=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_IMX6=y
|
||||
|
|
@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y
|
|||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CAN_FLEXCAN=y
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_RFKILL=y
|
||||
|
|
@ -160,6 +164,7 @@ CONFIG_SPI=y
|
|||
CONFIG_SPI_IMX=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_MC9S08DZ60=y
|
||||
CONFIG_GPIO_STMPE=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_IMX2_WDT=y
|
||||
|
|
@ -242,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y
|
|||
CONFIG_DMADEVICES=y
|
||||
CONFIG_IMX_SDMA=y
|
||||
CONFIG_MXS_DMA=y
|
||||
CONFIG_FSL_EDMA=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_DRM_IMX=y
|
||||
CONFIG_DRM_IMX_FB_HELPER=y
|
||||
|
|
@ -288,6 +294,7 @@ CONFIG_NLS_ASCII=y
|
|||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ CONFIG_ARCH_HIGHBANK=y
|
|||
CONFIG_ARCH_HI3xxx=y
|
||||
CONFIG_ARCH_KEYSTONE=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_TASKSTATS=y
|
||||
|
|
|
|||
|
|
@ -65,18 +65,8 @@ config IMX_HAVE_IOMUX_V1
|
|||
config ARCH_MXC_IOMUX_V3
|
||||
bool
|
||||
|
||||
config ARCH_MX1
|
||||
bool
|
||||
|
||||
config ARCH_MX25
|
||||
bool
|
||||
|
||||
config MACH_MX27
|
||||
bool
|
||||
|
||||
config SOC_IMX1
|
||||
bool
|
||||
select ARCH_MX1
|
||||
select CPU_ARM920T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
|
@ -89,7 +79,6 @@ config SOC_IMX21
|
|||
|
||||
config SOC_IMX25
|
||||
bool
|
||||
select ARCH_MX25
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select CPU_ARM926T
|
||||
select MXC_AVIC
|
||||
|
|
@ -100,7 +89,6 @@ config SOC_IMX27
|
|||
select ARCH_HAS_OPP
|
||||
select CPU_ARM926T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MACH_MX27
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX27
|
||||
|
||||
|
|
@ -119,18 +107,6 @@ config SOC_IMX35
|
|||
select PINCTRL_IMX35
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select MXC_TZIC
|
||||
|
||||
config SOC_IMX51
|
||||
bool
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
|
||||
if ARCH_MULTI_V4T
|
||||
|
||||
comment "MX1 platforms:"
|
||||
|
|
@ -366,15 +342,6 @@ config MACH_IMX27_VISSTRIM_M10
|
|||
This includes specific configurations for the board and its
|
||||
peripherals.
|
||||
|
||||
config MACH_IMX27LITE
|
||||
bool "LogicPD MX27 LITEKIT platform"
|
||||
select IMX_HAVE_PLATFORM_IMX_SSI
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select SOC_IMX27
|
||||
help
|
||||
Include support for MX27 LITEKIT platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_PCA100
|
||||
bool "Phytec phyCARD-s (pca100)"
|
||||
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
|
||||
|
|
@ -406,15 +373,6 @@ config MACH_MXT_TD60
|
|||
Include support for i-MXT (aka td60) platform. This
|
||||
includes specific configurations for the module and its peripherals.
|
||||
|
||||
config MACH_IMX27IPCAM
|
||||
bool "IMX27 IPCAM platform"
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select SOC_IMX27
|
||||
help
|
||||
Include support for IMX27 IPCAM platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_IMX27_DT
|
||||
bool "Support i.MX27 platforms from device tree"
|
||||
select SOC_IMX27
|
||||
|
|
@ -700,24 +658,29 @@ if ARCH_MULTI_V7
|
|||
|
||||
comment "Device tree only"
|
||||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select HAVE_IMX_SRC
|
||||
select MXC_TZIC
|
||||
|
||||
config SOC_IMX50
|
||||
bool "i.MX50 support"
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX50
|
||||
select SOC_IMX5
|
||||
|
||||
help
|
||||
This enables support for Freescale i.MX50 processor.
|
||||
|
||||
config MACH_IMX51_DT
|
||||
config SOC_IMX51
|
||||
bool "i.MX51 support"
|
||||
select SOC_IMX51
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
help
|
||||
This enables support for Freescale i.MX51 processor
|
||||
|
||||
config SOC_IMX53
|
||||
bool "i.MX53 support"
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX53
|
||||
select SOC_IMX5
|
||||
|
||||
|
|
@ -734,8 +697,6 @@ config SOC_IMX6
|
|||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select MFD_SYSCON
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
|
||||
config SOC_IMX6Q
|
||||
|
|
@ -771,8 +732,6 @@ config SOC_VF610
|
|||
select ARM_GIC
|
||||
select PINCTRL_VF610
|
||||
select VF_PIT_TIMER
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
|
||||
help
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
|
|||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
|
||||
|
||||
imx5-pm-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
|
||||
clk-pfd.o clk-busy.o clk.o \
|
||||
|
|
@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y)
|
|||
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
|
||||
# i.MX6SX reuses i.MX6Q cpuidle driver
|
||||
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SND_IMX_SOC
|
||||
|
|
@ -38,9 +40,6 @@ obj-y += ssi-fiq.o
|
|||
obj-y += ssi-fiq-ksym.o
|
||||
endif
|
||||
|
||||
# Support for CMOS sensor interface
|
||||
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
|
||||
|
||||
# i.MX1 based machines
|
||||
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
|
||||
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
|
||||
|
|
@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
|
|||
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
|
||||
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
|
||||
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
|
||||
obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
|
||||
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
|
||||
obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
|
||||
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
|
||||
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
|
||||
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
|
||||
obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
|
||||
|
||||
# i.MX31 based machines
|
||||
|
|
@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
|
|||
endif
|
||||
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
|
||||
|
||||
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
|
||||
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
|
||||
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
|
||||
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
|
||||
|
||||
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
|
||||
|
|
|
|||
|
|
@ -15,100 +15,103 @@
|
|||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx1-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
/* CCM register addresses */
|
||||
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
|
||||
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_PCDR IO_ADDR_CCM(0x20)
|
||||
|
||||
/* SCM register addresses */
|
||||
#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
|
||||
|
||||
#define SCM_GCCR IO_ADDR_SCM(0xc)
|
||||
|
||||
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
|
||||
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
|
||||
"prem", "fclk", };
|
||||
|
||||
enum imx1_clks {
|
||||
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
|
||||
spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
|
||||
uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
|
||||
usbd_gate, clk_max
|
||||
};
|
||||
static struct clk *clk[IMX1_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static void __iomem *ccm __initdata;
|
||||
#define CCM_CSCR (ccm + 0x0000)
|
||||
#define CCM_MPCTL0 (ccm + 0x0004)
|
||||
#define CCM_SPCTL0 (ccm + 0x000c)
|
||||
#define CCM_PCDR (ccm + 0x0020)
|
||||
#define SCM_GCCR (ccm + 0x0810)
|
||||
|
||||
static void __init _mx1_clocks_init(unsigned long fref)
|
||||
{
|
||||
clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
|
||||
clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
|
||||
clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
|
||||
clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
|
||||
clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
|
||||
clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
|
||||
clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
|
||||
clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
|
||||
clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
|
||||
clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
|
||||
clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
|
||||
clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
|
||||
clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
|
||||
clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
|
||||
clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
|
||||
clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
|
||||
clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
|
||||
clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
|
||||
clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
|
||||
clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
}
|
||||
|
||||
int __init mx1_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[clk32] = imx_clk_fixed("clk32", fref);
|
||||
clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
|
||||
clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
|
||||
clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
|
||||
clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
|
||||
ARRAY_SIZE(prem_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
|
||||
clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
|
||||
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
|
||||
clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
|
||||
clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
|
||||
clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
|
||||
clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
|
||||
clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
|
||||
ARRAY_SIZE(clko_sel_clks));
|
||||
clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
|
||||
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
|
||||
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
|
||||
clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
|
||||
clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
|
||||
clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
|
||||
_mx1_clocks_init(fref);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("imx1 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
|
||||
|
||||
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx1_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
ccm = of_iomap(np, 0);
|
||||
BUG_ON(!ccm);
|
||||
|
||||
_mx1_clocks_init(32768);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
|
||||
|
|
|
|||
|
|
@ -7,178 +7,165 @@
|
|||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx21-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
|
||||
static void __iomem *ccm __initdata;
|
||||
|
||||
/* Register offsets */
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
|
||||
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
|
||||
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
|
||||
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
|
||||
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
|
||||
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
|
||||
#define CCM_CCSR IO_ADDR_CCM(0x28)
|
||||
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
|
||||
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
|
||||
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
|
||||
#define CCM_CSCR (ccm + 0x00)
|
||||
#define CCM_MPCTL0 (ccm + 0x04)
|
||||
#define CCM_SPCTL0 (ccm + 0x0c)
|
||||
#define CCM_PCDR0 (ccm + 0x18)
|
||||
#define CCM_PCDR1 (ccm + 0x1c)
|
||||
#define CCM_PCCR0 (ccm + 0x20)
|
||||
#define CCM_PCCR1 (ccm + 0x24)
|
||||
|
||||
static const char *mpll_sel_clks[] = { "fpm", "ckih", };
|
||||
static const char *spll_sel_clks[] = { "fpm", "ckih", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
|
||||
static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
|
||||
static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
|
||||
static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
|
||||
|
||||
enum imx21_clks {
|
||||
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
|
||||
per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
|
||||
uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
|
||||
pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
|
||||
lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
|
||||
per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
|
||||
ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
|
||||
emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
|
||||
gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
|
||||
};
|
||||
static struct clk *clk[IMX21_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
|
||||
{
|
||||
BUG_ON(!ccm);
|
||||
|
||||
clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
|
||||
clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
|
||||
clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
|
||||
clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
|
||||
|
||||
clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
|
||||
clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
|
||||
clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
|
||||
clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
|
||||
clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
|
||||
clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
|
||||
|
||||
clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
|
||||
clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
|
||||
|
||||
clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
|
||||
clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
|
||||
clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
|
||||
clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
|
||||
clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
|
||||
clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
|
||||
|
||||
clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
|
||||
clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
|
||||
clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
|
||||
clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
|
||||
clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
|
||||
clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
|
||||
clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
|
||||
clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
|
||||
clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
|
||||
clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
|
||||
clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
|
||||
clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
|
||||
clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
|
||||
|
||||
clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
|
||||
clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
}
|
||||
|
||||
/*
|
||||
* must be called very early to get information about the
|
||||
* available clock rate when the timer framework starts
|
||||
*/
|
||||
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
|
||||
{
|
||||
int i;
|
||||
ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
|
||||
|
||||
clk[ckil] = imx_clk_fixed("ckil", lref);
|
||||
clk[ckih] = imx_clk_fixed("ckih", href);
|
||||
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
|
||||
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
|
||||
ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
|
||||
ARRAY_SIZE(spll_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
|
||||
clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
|
||||
clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
|
||||
clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
|
||||
clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
|
||||
clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
|
||||
clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
|
||||
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
|
||||
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
|
||||
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
|
||||
clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
|
||||
clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
|
||||
clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
|
||||
clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
|
||||
clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
|
||||
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
|
||||
clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
|
||||
clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
|
||||
clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
|
||||
clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
|
||||
_mx21_clocks_init(lref, href);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX21 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[per1], "per1", NULL);
|
||||
clk_register_clkdev(clk[per2], "per2", NULL);
|
||||
clk_register_clkdev(clk[per3], "per3", NULL);
|
||||
clk_register_clkdev(clk[per4], "per4", NULL);
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
|
||||
clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
|
||||
clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
|
||||
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
|
||||
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[brom_gate], "brom", NULL);
|
||||
clk_register_clkdev(clk[emma_gate], "emma", NULL);
|
||||
clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
|
||||
clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
|
||||
clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
|
||||
clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
|
||||
clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
|
||||
clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
|
||||
clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
|
||||
clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
|
||||
|
||||
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx21_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
ccm = of_iomap(np, 0);
|
||||
|
||||
_mx21_clocks_init(32768, 26000000);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
|
||||
|
|
|
|||
|
|
@ -32,8 +32,6 @@
|
|||
#include "hardware.h"
|
||||
#include "mx25.h"
|
||||
|
||||
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
|
||||
|
||||
#define CCM_MPCTL 0x00
|
||||
#define CCM_UPCTL 0x04
|
||||
#define CCM_CCTL 0x08
|
||||
|
|
@ -56,7 +54,7 @@
|
|||
#define CCM_LTR3 0x4c
|
||||
#define CCM_MCR 0x64
|
||||
|
||||
#define ccm(x) (CRM_BASE + (x))
|
||||
#define ccm(x) (ccm_base + (x))
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
|
|
@ -91,9 +89,10 @@ enum mx25_clks {
|
|||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static int __init __mx25_clocks_init(unsigned long osc_rate)
|
||||
static int __init __mx25_clocks_init(unsigned long osc_rate,
|
||||
void __iomem *ccm_base)
|
||||
{
|
||||
int i;
|
||||
BUG_ON(!ccm_base);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[osc] = imx_clk_fixed("osc", osc_rate);
|
||||
|
|
@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
|
|||
/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
|
||||
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX25 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb]);
|
||||
|
||||
/* Clock source for gpt must be derived from AHB */
|
||||
clk_set_parent(clk[per5_sel], clk[ahb]);
|
||||
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO parent as ipg, since this configuration
|
||||
* is used on some imx25 board designs to clock the audio codec.
|
||||
|
|
@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
|
|||
|
||||
int __init mx25_clocks_init(void)
|
||||
{
|
||||
__mx25_clocks_init(24000000);
|
||||
void __iomem *ccm;
|
||||
|
||||
ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
|
||||
|
||||
__mx25_clocks_init(24000000, ccm);
|
||||
|
||||
clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
/* i.mx25 has the i.mx21 type uart */
|
||||
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
|
||||
|
|
@ -314,29 +313,27 @@ int __init mx25_clocks_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int __init mx25_clocks_init_dt(void)
|
||||
static void __init mx25_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device_node *refnp;
|
||||
unsigned long osc_rate = 24000000;
|
||||
void __iomem *ccm;
|
||||
|
||||
/* retrieve the freqency of fixed clocks from device tree */
|
||||
for_each_compatible_node(np, NULL, "fixed-clock") {
|
||||
for_each_compatible_node(refnp, NULL, "fixed-clock") {
|
||||
u32 rate;
|
||||
if (of_property_read_u32(np, "clock-frequency", &rate))
|
||||
if (of_property_read_u32(refnp, "clock-frequency", &rate))
|
||||
continue;
|
||||
|
||||
if (of_device_is_compatible(np, "fsl,imx-osc"))
|
||||
if (of_device_is_compatible(refnp, "fsl,imx-osc"))
|
||||
osc_rate = rate;
|
||||
}
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
|
||||
ccm = of_iomap(np, 0);
|
||||
__mx25_clocks_init(osc_rate, ccm);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
__mx25_clocks_init(osc_rate);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
|
||||
|
||||
return 0;
|
||||
}
|
||||
CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
|
||||
|
|
|
|||
|
|
@ -1,61 +1,36 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx27-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
|
||||
static void __iomem *ccm __initdata;
|
||||
|
||||
/* Register offsets */
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
|
||||
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
|
||||
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
|
||||
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
|
||||
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
|
||||
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
|
||||
#define CCM_CCSR IO_ADDR_CCM(0x28)
|
||||
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
|
||||
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
|
||||
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
|
||||
|
||||
#define CCM_CSCR_UPDATE_DIS (1 << 31)
|
||||
#define CCM_CSCR_SSI2 (1 << 23)
|
||||
#define CCM_CSCR_SSI1 (1 << 22)
|
||||
#define CCM_CSCR_VPU (1 << 21)
|
||||
#define CCM_CSCR_MSHC (1 << 20)
|
||||
#define CCM_CSCR_SPLLRES (1 << 19)
|
||||
#define CCM_CSCR_MPLLRES (1 << 18)
|
||||
#define CCM_CSCR_SP (1 << 17)
|
||||
#define CCM_CSCR_MCU (1 << 16)
|
||||
#define CCM_CSCR_OSC26MDIV (1 << 4)
|
||||
#define CCM_CSCR_OSC26M (1 << 3)
|
||||
#define CCM_CSCR_FPM (1 << 2)
|
||||
#define CCM_CSCR_SPEN (1 << 1)
|
||||
#define CCM_CSCR_MPEN (1 << 0)
|
||||
|
||||
/* i.MX27 TO 2+ */
|
||||
#define CCM_CSCR_ARM_SRC (1 << 15)
|
||||
|
||||
#define CCM_SPCTL1_LF (1 << 15)
|
||||
#define CCM_SPCTL1_BRMO (1 << 6)
|
||||
#define CCM_CSCR (ccm + 0x00)
|
||||
#define CCM_MPCTL0 (ccm + 0x04)
|
||||
#define CCM_MPCTL1 (ccm + 0x08)
|
||||
#define CCM_SPCTL0 (ccm + 0x0c)
|
||||
#define CCM_SPCTL1 (ccm + 0x10)
|
||||
#define CCM_PCDR0 (ccm + 0x18)
|
||||
#define CCM_PCDR1 (ccm + 0x1c)
|
||||
#define CCM_PCCR0 (ccm + 0x20)
|
||||
#define CCM_PCCR1 (ccm + 0x24)
|
||||
#define CCM_CCSR (ccm + 0x28)
|
||||
|
||||
static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
|
||||
static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
|
||||
static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
|
||||
static const char *clko_sel_clks[] = {
|
||||
"ckil", "fpm", "ckih", "ckih",
|
||||
"ckih", "mpll", "spll", "cpu_div",
|
||||
"ckil", "fpm", "ckih_gate", "ckih_gate",
|
||||
"ckih_gate", "mpll", "spll", "cpu_div",
|
||||
"ahb", "ipg", "per1_div", "per2_div",
|
||||
"per3_div", "per4_div", "ssi1_div", "ssi2_div",
|
||||
"nfc_div", "mshc_div", "vpu_div", "60m",
|
||||
|
|
@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
|
|||
|
||||
static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
|
||||
|
||||
enum mx27_clks {
|
||||
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
|
||||
per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
|
||||
clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
|
||||
clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
|
||||
sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
|
||||
rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
|
||||
kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
|
||||
gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
|
||||
gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
|
||||
emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
|
||||
cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
|
||||
vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
|
||||
usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
|
||||
vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
|
||||
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
|
||||
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
|
||||
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
|
||||
mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
|
||||
rtic_ahb_gate, mshc_baud_gate, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk *clk[IMX27_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init _mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
BUG_ON(!ccm);
|
||||
|
||||
clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
|
||||
clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
|
||||
clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
|
||||
clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
|
||||
clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
|
||||
clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
|
||||
clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
||||
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
|
||||
clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
|
||||
} else {
|
||||
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
|
||||
clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
|
||||
}
|
||||
|
||||
clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
|
||||
clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
|
||||
clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
|
||||
clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
|
||||
clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
|
||||
clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
||||
clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
||||
clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
||||
clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
|
||||
clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||
clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
||||
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
|
||||
else
|
||||
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
|
||||
|
||||
clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
|
||||
clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
|
||||
clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
|
||||
clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
|
||||
clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
|
||||
clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
|
||||
clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
|
||||
clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
|
||||
clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
|
||||
clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
|
||||
clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
|
||||
clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
|
||||
clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
|
||||
clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
|
||||
|
||||
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
}
|
||||
|
||||
int __init mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
struct device_node *np;
|
||||
ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckih] = imx_clk_fixed("ckih", fref);
|
||||
clk[ckil] = imx_clk_fixed("ckil", 32768);
|
||||
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
|
||||
clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
|
||||
_mx27_clocks_init(fref);
|
||||
|
||||
clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
|
||||
mpll_osc_sel_clks,
|
||||
ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
|
||||
ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
|
||||
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
||||
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
|
||||
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
|
||||
} else {
|
||||
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
|
||||
}
|
||||
|
||||
clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
|
||||
clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
|
||||
clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
|
||||
clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
|
||||
clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
|
||||
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
||||
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
||||
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
|
||||
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
||||
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
|
||||
else
|
||||
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
|
||||
clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
|
||||
clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
|
||||
clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
|
||||
clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
|
||||
clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
|
||||
clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
|
||||
clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
|
||||
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
|
||||
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
|
||||
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
|
||||
clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
|
||||
clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
|
||||
clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
|
||||
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
|
||||
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX27 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
|
||||
if (np) {
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
|
||||
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb_gate]);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mx27_clocks_init_dt(void)
|
||||
static void __init mx27_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device_node *refnp;
|
||||
u32 fref = 26000000; /* default */
|
||||
|
||||
for_each_compatible_node(np, NULL, "fixed-clock") {
|
||||
if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
|
||||
for_each_compatible_node(refnp, NULL, "fixed-clock") {
|
||||
if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
|
||||
continue;
|
||||
|
||||
if (!of_property_read_u32(np, "clock-frequency", &fref))
|
||||
if (!of_property_read_u32(refnp, "clock-frequency", &fref))
|
||||
break;
|
||||
}
|
||||
|
||||
return mx27_clocks_init(fref);
|
||||
ccm = of_iomap(np, 0);
|
||||
|
||||
_mx27_clocks_init(fref);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
|
||||
|
|
|
|||
|
|
@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
|
|||
int __init mx31_clocks_init(unsigned long fref)
|
||||
{
|
||||
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
|
||||
int i;
|
||||
struct device_node *np;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
|
|
@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
|
||||
clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("imx31 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
|
||||
|
||||
|
|
|
|||
|
|
@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
|
|||
u32 pdr0, consumer_sel, hsp_sel;
|
||||
struct arm_ahb_div *aad;
|
||||
unsigned char *hsp_div;
|
||||
u32 i;
|
||||
|
||||
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
|
||||
consumer_sel = (pdr0 >> 16) & 0xf;
|
||||
|
|
@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
|
|||
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
|
||||
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX35 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
|
||||
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
|
||||
|
|
|
|||
|
|
@ -18,11 +18,54 @@
|
|||
#include <linux/of_irq.h>
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
#include "crm-regs-imx5.h"
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define MX51_DPLL1_BASE 0x83f80000
|
||||
#define MX51_DPLL2_BASE 0x83f84000
|
||||
#define MX51_DPLL3_BASE 0x83f88000
|
||||
|
||||
#define MX53_DPLL1_BASE 0x63f80000
|
||||
#define MX53_DPLL2_BASE 0x63f84000
|
||||
#define MX53_DPLL3_BASE 0x63f88000
|
||||
#define MX53_DPLL4_BASE 0x63f8c000
|
||||
|
||||
#define MXC_CCM_CCR (ccm_base + 0x00)
|
||||
#define MXC_CCM_CCDR (ccm_base + 0x04)
|
||||
#define MXC_CCM_CSR (ccm_base + 0x08)
|
||||
#define MXC_CCM_CCSR (ccm_base + 0x0c)
|
||||
#define MXC_CCM_CACRR (ccm_base + 0x10)
|
||||
#define MXC_CCM_CBCDR (ccm_base + 0x14)
|
||||
#define MXC_CCM_CBCMR (ccm_base + 0x18)
|
||||
#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
|
||||
#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
|
||||
#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
|
||||
#define MXC_CCM_CS1CDR (ccm_base + 0x28)
|
||||
#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
|
||||
#define MXC_CCM_CDCDR (ccm_base + 0x30)
|
||||
#define MXC_CCM_CHSCDR (ccm_base + 0x34)
|
||||
#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
|
||||
#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
|
||||
#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
|
||||
#define MXC_CCM_CWDR (ccm_base + 0x44)
|
||||
#define MXC_CCM_CDHIPR (ccm_base + 0x48)
|
||||
#define MXC_CCM_CDCR (ccm_base + 0x4c)
|
||||
#define MXC_CCM_CTOR (ccm_base + 0x50)
|
||||
#define MXC_CCM_CLPCR (ccm_base + 0x54)
|
||||
#define MXC_CCM_CISR (ccm_base + 0x58)
|
||||
#define MXC_CCM_CIMR (ccm_base + 0x5c)
|
||||
#define MXC_CCM_CCOSR (ccm_base + 0x60)
|
||||
#define MXC_CCM_CGPR (ccm_base + 0x64)
|
||||
#define MXC_CCM_CCGR0 (ccm_base + 0x68)
|
||||
#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
|
||||
#define MXC_CCM_CCGR2 (ccm_base + 0x70)
|
||||
#define MXC_CCM_CCGR3 (ccm_base + 0x74)
|
||||
#define MXC_CCM_CCGR4 (ccm_base + 0x78)
|
||||
#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
|
||||
#define MXC_CCM_CCGR6 (ccm_base + 0x80)
|
||||
#define MXC_CCM_CCGR7 (ccm_base + 0x84)
|
||||
|
||||
/* Low-power Audio Playback Mode clock */
|
||||
static const char *lp_apm_sel[] = { "osc", };
|
||||
|
||||
|
|
@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
|
|||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
unsigned long rate_osc, unsigned long rate_ckih1,
|
||||
unsigned long rate_ckih2)
|
||||
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
||||
{
|
||||
int i;
|
||||
imx5_pm_set_ccm_base(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
|
||||
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
|
||||
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
|
||||
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
|
||||
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
|
||||
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
|
||||
|
||||
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
|
|
@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
|
||||
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX5 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
|
@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
|
||||
static void __init mx50_clocks_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
unsigned long r;
|
||||
int i;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
|
|
@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
|
|||
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
|
||||
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX50 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
|
|
@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
|
|||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
|
||||
|
||||
int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
unsigned long rate_ckih1, unsigned long rate_ckih2)
|
||||
static void __init mx51_clocks_init(struct device_node *np)
|
||||
{
|
||||
int i;
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
u32 val;
|
||||
struct device_node *np;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
|
||||
pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
|
|
@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
|
||||
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX51 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
|
||||
|
||||
/* set the usboh3 parent to pll2_sw */
|
||||
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
|
|
@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX51", mx51_revision());
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
|
|
@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
val = readl(MXC_CCM_CLPCR);
|
||||
val |= 1 << 23;
|
||||
writel(val, MXC_CCM_CLPCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx51_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
mx51_clocks_init(0, 0, 0, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
|
||||
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
|
||||
|
||||
static void __init mx53_clocks_init(struct device_node *np)
|
||||
{
|
||||
int i;
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
unsigned long r;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
|
||||
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
|
|
@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
|
|||
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX53 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
|
|
@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
|
|||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
|
|
@ -70,51 +71,16 @@ static const char *cko_sels[] = { "cko1", "cko2", };
|
|||
static const char *lvds_sels[] = {
|
||||
"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
|
||||
"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
|
||||
"pcie_ref", "sata_ref",
|
||||
"pcie_ref_125m", "sata_ref_100m",
|
||||
};
|
||||
|
||||
enum mx6q_clks {
|
||||
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
|
||||
pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
|
||||
pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
|
||||
periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
|
||||
esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
|
||||
gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
|
||||
ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
|
||||
ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
|
||||
ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
|
||||
usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
|
||||
emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
|
||||
periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
|
||||
asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
|
||||
gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
|
||||
ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
|
||||
ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
|
||||
ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
|
||||
usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
|
||||
emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
|
||||
mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
|
||||
can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
|
||||
esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
|
||||
hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
|
||||
ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
|
||||
mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
|
||||
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
|
||||
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
|
||||
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
|
||||
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
|
||||
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
|
||||
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
|
||||
usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
|
||||
spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
|
||||
lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk *clk[IMX6QDL_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, rom, arm,
|
||||
static unsigned int const clks_init_on[] __initconst = {
|
||||
IMX6QDL_CLK_MMDC_CH0_AXI,
|
||||
IMX6QDL_CLK_ROM,
|
||||
IMX6QDL_CLK_ARM,
|
||||
};
|
||||
|
||||
static struct clk_div_table clk_enet_ref_table[] = {
|
||||
|
|
@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
int i;
|
||||
int ret;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[osc] = imx_obtain_fixed_clock("osc", 0);
|
||||
clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
video_div_table[2].div = 1;
|
||||
};
|
||||
|
||||
/* type name parent_name base div_mask */
|
||||
clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
|
||||
clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
|
||||
clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
|
||||
clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
|
||||
clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
|
||||
clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
|
||||
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
|
||||
/* type name parent_name base div_mask */
|
||||
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
|
||||
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
|
||||
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
|
||||
|
||||
/*
|
||||
* Bit 20 is the reserved and read-only bit, we do this only for:
|
||||
|
|
@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
* - Keep refcount when do usbphy clk_enable/disable, in that case,
|
||||
* the clk framework may need to enable/disable usbphy's parent
|
||||
*/
|
||||
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
|
||||
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
|
||||
clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
|
||||
clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
|
||||
|
||||
/*
|
||||
* usbphy*_gate needs to be on after system boots up, and software
|
||||
* never needs to control it anymore.
|
||||
*/
|
||||
clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
|
||||
clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
|
||||
clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
|
||||
clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
|
||||
|
||||
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
|
||||
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
|
||||
clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
|
||||
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
|
||||
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
|
||||
&imx_ccm_lock);
|
||||
|
||||
clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
|
||||
/*
|
||||
* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
|
||||
|
|
@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
* the "output_enable" bit as a gate, even though it's really just
|
||||
* enabling clock output.
|
||||
*/
|
||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
/* name parent_name reg idx */
|
||||
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
|
||||
/* name parent_name mult div */
|
||||
clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
/* name parent_name mult div */
|
||||
clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
|
||||
clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
|
|
@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
imx6q_pm_set_ccm_base(base);
|
||||
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
/* name parent_name reg shift width */
|
||||
clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
/* name parent_name reg shift width */
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
/* name parent_name reg shift */
|
||||
clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
/* name parent_name reg shift */
|
||||
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
if (cpu_is_imx6dl())
|
||||
/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
|
||||
clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
else
|
||||
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of imx6q clock gpu3d_shader get
|
||||
* redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
|
||||
*/
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
else
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of the imx6q clock gpu2d get
|
||||
* redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
|
||||
*/
|
||||
clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
else
|
||||
clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX6q clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
|
||||
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
|
||||
|
||||
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
|
||||
cpu_is_imx6dl()) {
|
||||
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
}
|
||||
|
||||
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
|
||||
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
|
||||
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
|
||||
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
|
||||
|
||||
/*
|
||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||
* So choose pll2_pfd2_396m as enfc_sel's parent.
|
||||
*/
|
||||
clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clk_prepare_enable(clk[usbphy1_gate]);
|
||||
clk_prepare_enable(clk[usbphy2_gate]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO with OSC24M, since this configuration
|
||||
* is widely used by imx6q board designs to clock audio codec.
|
||||
*/
|
||||
ret = clk_set_parent(clk[cko2_sel], clk[osc]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
|
||||
if (!ret)
|
||||
ret = clk_set_parent(clk[cko], clk[cko2]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
|
||||
|
||||
/* All existing boards with PCIe use LVDS1 */
|
||||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
|
||||
|
|
|
|||
|
|
@ -348,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX6SL clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
|
||||
|
||||
/* Ensure the AHB clk is at 132MHz. */
|
||||
ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
|
||||
if (ret)
|
||||
|
|
@ -383,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
|
||||
mxc_timer_init_dt(np);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
|
||||
|
|
|
|||
|
|
@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = {
|
|||
static u32 share_count_asrc;
|
||||
static u32 share_count_audio;
|
||||
static u32 share_count_esai;
|
||||
static u32 share_count_ssi1;
|
||||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
|
|
@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
|
||||
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
|
||||
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
|
||||
clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28);
|
||||
|
|
@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
/* mask handshake of mmdc */
|
||||
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
|
|
@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
|
||||
mxc_timer_init_dt(np);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
|
||||
|
|
|
|||
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