iwlagn: Remove dependence of iwl_priv from eeprom routines.
Make the eeprom routines less dependent on the iwl_priv structure. Don't use the priv when bus structure is sufficient. Signed-off-by: Don Fry <donald.h.fry@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Don Fry
John W. Linville
Родитель
383b0874ab
Коммит
1431b2166a
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@ -149,23 +149,23 @@ static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
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* EEPROM chip, not a single event, so even reads could conflict if they
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* weren't arbitrated by the semaphore.
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*/
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static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
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static int iwl_eeprom_acquire_semaphore(struct iwl_bus *bus)
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{
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u16 count;
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int ret;
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for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
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/* Request semaphore */
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iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
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iwl_set_bit(bus, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
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/* See if we got it */
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ret = iwl_poll_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
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ret = iwl_poll_bit(bus, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
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EEPROM_SEM_TIMEOUT);
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if (ret >= 0) {
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IWL_DEBUG_EEPROM(priv,
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IWL_DEBUG_EEPROM(bus,
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"Acquired semaphore after %d tries.\n",
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count+1);
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return ret;
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@ -175,9 +175,9 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
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return ret;
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}
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static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
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static void iwl_eeprom_release_semaphore(struct iwl_bus *bus)
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{
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iwl_clear_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
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iwl_clear_bit(bus, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
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}
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@ -302,19 +302,19 @@ void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
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*
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******************************************************************************/
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static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
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static void iwl_set_otp_access(struct iwl_bus *bus, enum iwl_access_mode mode)
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{
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iwl_read32(bus(priv), CSR_OTP_GP_REG);
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iwl_read32(bus, CSR_OTP_GP_REG);
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if (mode == IWL_OTP_ACCESS_ABSOLUTE)
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iwl_clear_bit(bus(priv), CSR_OTP_GP_REG,
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iwl_clear_bit(bus, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_OTP_ACCESS_MODE);
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else
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iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
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iwl_set_bit(bus, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_OTP_ACCESS_MODE);
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}
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static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
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static int iwl_get_nvm_type(struct iwl_bus *bus, u32 hw_rev)
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{
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u32 otpgp;
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int nvm_type;
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@ -322,7 +322,7 @@ static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
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/* OTP only valid for CP/PP and after */
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switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_NONE:
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IWL_ERR(priv, "Unknown hardware type\n");
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IWL_ERR(bus, "Unknown hardware type\n");
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return -ENOENT;
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case CSR_HW_REV_TYPE_5300:
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case CSR_HW_REV_TYPE_5350:
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@ -331,7 +331,7 @@ static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
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nvm_type = NVM_DEVICE_TYPE_EEPROM;
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break;
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default:
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otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
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otpgp = iwl_read32(bus, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
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nvm_type = NVM_DEVICE_TYPE_OTP;
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else
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@ -341,73 +341,73 @@ static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
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return nvm_type;
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}
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static int iwl_init_otp_access(struct iwl_priv *priv)
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static int iwl_init_otp_access(struct iwl_bus *bus)
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{
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int ret;
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/* Enable 40MHz radio clock */
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iwl_write32(bus(priv), CSR_GP_CNTRL,
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iwl_read32(bus(priv), CSR_GP_CNTRL) |
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iwl_write32(bus, CSR_GP_CNTRL,
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iwl_read32(bus, CSR_GP_CNTRL) |
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/* wait for clock to be ready */
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ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
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ret = iwl_poll_bit(bus, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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25000);
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if (ret < 0)
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IWL_ERR(priv, "Time out access OTP\n");
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IWL_ERR(bus, "Time out access OTP\n");
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else {
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iwl_set_bits_prph(bus(priv), APMG_PS_CTRL_REG,
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iwl_set_bits_prph(bus, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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udelay(5);
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iwl_clear_bits_prph(bus(priv), APMG_PS_CTRL_REG,
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iwl_clear_bits_prph(bus, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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/*
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* CSR auto clock gate disable bit -
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* this is only applicable for HW with OTP shadow RAM
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*/
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if (priv->cfg->base_params->shadow_ram_support)
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iwl_set_bit(bus(priv), CSR_DBG_LINK_PWR_MGMT_REG,
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if (priv(bus)->cfg->base_params->shadow_ram_support)
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iwl_set_bit(bus, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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}
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return ret;
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}
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static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data)
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static int iwl_read_otp_word(struct iwl_bus *bus, u16 addr, __le16 *eeprom_data)
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{
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int ret = 0;
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u32 r;
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u32 otpgp;
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iwl_write32(bus(priv), CSR_EEPROM_REG,
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iwl_write32(bus, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
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ret = iwl_poll_bit(bus, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
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IWL_ERR(bus, "Time out reading OTP[%d]\n", addr);
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return ret;
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}
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r = iwl_read32(bus(priv), CSR_EEPROM_REG);
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r = iwl_read32(bus, CSR_EEPROM_REG);
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/* check for ECC errors: */
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otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
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otpgp = iwl_read32(bus, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
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/* stop in this case */
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/* set the uncorrectable OTP ECC bit for acknowledgement */
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iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
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iwl_set_bit(bus, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
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IWL_ERR(bus, "Uncorrectable OTP ECC error, abort OTP read\n");
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return -EINVAL;
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}
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if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
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/* continue in this case */
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/* set the correctable OTP ECC bit for acknowledgement */
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iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
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iwl_set_bit(bus, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
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IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
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IWL_ERR(bus, "Correctable OTP ECC error, continue read\n");
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}
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*eeprom_data = cpu_to_le16(r >> 16);
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return 0;
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@ -416,20 +416,20 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
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/*
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* iwl_is_otp_empty: check for empty OTP
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*/
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static bool iwl_is_otp_empty(struct iwl_priv *priv)
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static bool iwl_is_otp_empty(struct iwl_bus *bus)
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{
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u16 next_link_addr = 0;
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__le16 link_value;
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bool is_empty = false;
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/* locate the beginning of OTP link list */
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if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
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if (!iwl_read_otp_word(bus, next_link_addr, &link_value)) {
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if (!link_value) {
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IWL_ERR(priv, "OTP is empty\n");
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IWL_ERR(bus, "OTP is empty\n");
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is_empty = true;
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}
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} else {
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IWL_ERR(priv, "Unable to read first block of OTP list.\n");
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IWL_ERR(bus, "Unable to read first block of OTP list.\n");
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is_empty = true;
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}
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@ -446,7 +446,7 @@ static bool iwl_is_otp_empty(struct iwl_priv *priv)
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* we should read and used to configure the device.
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* only perform this operation if shadow RAM is disabled
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*/
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static int iwl_find_otp_image(struct iwl_priv *priv,
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static int iwl_find_otp_image(struct iwl_bus *bus,
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u16 *validblockaddr)
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{
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u16 next_link_addr = 0, valid_addr;
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@ -454,10 +454,10 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
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int usedblocks = 0;
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/* set addressing mode to absolute to traverse the link list */
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iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
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iwl_set_otp_access(bus, IWL_OTP_ACCESS_ABSOLUTE);
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/* checking for empty OTP or error */
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if (iwl_is_otp_empty(priv))
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if (iwl_is_otp_empty(bus))
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return -EINVAL;
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/*
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@ -471,9 +471,9 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
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*/
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valid_addr = next_link_addr;
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next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
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IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n",
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IWL_DEBUG_EEPROM(bus, "OTP blocks %d addr 0x%x\n",
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usedblocks, next_link_addr);
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if (iwl_read_otp_word(priv, next_link_addr, &link_value))
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if (iwl_read_otp_word(bus, next_link_addr, &link_value))
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return -EINVAL;
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if (!link_value) {
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/*
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@ -488,10 +488,10 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
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}
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/* more in the link list, continue */
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usedblocks++;
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} while (usedblocks <= priv->cfg->base_params->max_ll_items);
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} while (usedblocks <= priv(bus)->cfg->base_params->max_ll_items);
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/* OTP has no valid blocks */
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IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n");
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IWL_DEBUG_EEPROM(bus, "OTP has no valid blocks\n");
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return -EINVAL;
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}
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@ -504,28 +504,28 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
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* iwl_get_max_txpower_avg - get the highest tx power from all chains.
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* find the highest tx power from all chains for the channel
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*/
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static s8 iwl_get_max_txpower_avg(struct iwl_priv *priv,
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static s8 iwl_get_max_txpower_avg(struct iwl_cfg *cfg,
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struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
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int element, s8 *max_txpower_in_half_dbm)
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{
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s8 max_txpower_avg = 0; /* (dBm) */
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/* Take the highest tx power from any valid chains */
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if ((priv->cfg->valid_tx_ant & ANT_A) &&
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if ((cfg->valid_tx_ant & ANT_A) &&
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(enhanced_txpower[element].chain_a_max > max_txpower_avg))
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max_txpower_avg = enhanced_txpower[element].chain_a_max;
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if ((priv->cfg->valid_tx_ant & ANT_B) &&
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if ((cfg->valid_tx_ant & ANT_B) &&
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(enhanced_txpower[element].chain_b_max > max_txpower_avg))
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max_txpower_avg = enhanced_txpower[element].chain_b_max;
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if ((priv->cfg->valid_tx_ant & ANT_C) &&
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if ((cfg->valid_tx_ant & ANT_C) &&
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(enhanced_txpower[element].chain_c_max > max_txpower_avg))
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max_txpower_avg = enhanced_txpower[element].chain_c_max;
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if (((priv->cfg->valid_tx_ant == ANT_AB) |
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(priv->cfg->valid_tx_ant == ANT_BC) |
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(priv->cfg->valid_tx_ant == ANT_AC)) &&
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if (((cfg->valid_tx_ant == ANT_AB) |
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(cfg->valid_tx_ant == ANT_BC) |
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(cfg->valid_tx_ant == ANT_AC)) &&
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(enhanced_txpower[element].mimo2_max > max_txpower_avg))
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max_txpower_avg = enhanced_txpower[element].mimo2_max;
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if ((priv->cfg->valid_tx_ant == ANT_ABC) &&
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if ((cfg->valid_tx_ant == ANT_ABC) &&
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(enhanced_txpower[element].mimo3_max > max_txpower_avg))
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max_txpower_avg = enhanced_txpower[element].mimo3_max;
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@ -627,7 +627,7 @@ void iwl_eeprom_enhanced_txpower(struct iwl_priv *priv)
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((txp->delta_20_in_40 & 0xf0) >> 4),
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(txp->delta_20_in_40 & 0x0f));
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max_txp_avg = iwl_get_max_txpower_avg(priv, txp_array, idx,
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max_txp_avg = iwl_get_max_txpower_avg(priv->cfg, txp_array, idx,
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&max_txp_avg_halfdbm);
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/*
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@ -660,7 +660,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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u16 validblockaddr = 0;
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u16 cache_addr = 0;
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priv->nvm_device_type = iwl_get_nvm_type(priv, hw_rev);
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priv->nvm_device_type = iwl_get_nvm_type(bus(priv), hw_rev);
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if (priv->nvm_device_type == -ENOENT)
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return -ENOENT;
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/* allocate eeprom */
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@ -683,7 +683,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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}
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/* Make sure driver (instead of uCode) is allowed to read EEPROM */
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ret = iwl_eeprom_acquire_semaphore(priv);
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ret = iwl_eeprom_acquire_semaphore(bus(priv));
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if (ret < 0) {
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IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
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ret = -ENOENT;
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@ -692,7 +692,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
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ret = iwl_init_otp_access(priv);
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ret = iwl_init_otp_access(bus(priv));
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if (ret) {
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IWL_ERR(priv, "Failed to initialize OTP access.\n");
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ret = -ENOENT;
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@ -707,7 +707,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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/* traversing the linked list if no shadow ram supported */
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if (!priv->cfg->base_params->shadow_ram_support) {
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if (iwl_find_otp_image(priv, &validblockaddr)) {
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if (iwl_find_otp_image(bus(priv), &validblockaddr)) {
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ret = -ENOENT;
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goto done;
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}
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@ -716,7 +716,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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addr += sizeof(u16)) {
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__le16 eeprom_data;
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ret = iwl_read_otp_word(priv, addr, &eeprom_data);
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ret = iwl_read_otp_word(bus(priv), addr, &eeprom_data);
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if (ret)
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goto done;
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e[cache_addr / 2] = eeprom_data;
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@ -750,7 +750,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
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ret = 0;
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done:
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iwl_eeprom_release_semaphore(priv);
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iwl_eeprom_release_semaphore(bus(priv));
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err:
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if (ret)
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|
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