PCI: pci-bridge-emul: Eliminate the 'reserved' member
Per PCIe 5.0 r1.0, Terms and Acronyms, Page 80: Reserved register fields must be read only and must return 0 (all 0's for multi-bit fields) when read. Reserved encodings for register and packet fields must not be used. Any implementation dependence on a Reserved field value or encoding will result in an implementation that is not PCI Express-compliant. This patch ensures reads will return 0 for any bit not in the Read-Only, Read-Write, or Write-1-to-Clear bitmasks. Link: https://lore.kernel.org/r/20200511162117.6674-5-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
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@ -24,6 +24,17 @@
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#define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
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#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
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/**
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* struct pci_bridge_reg_behavior - register bits behaviors
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* @ro: Read-Only bits
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* @rw: Read-Write bits
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* @w1c: Write-1-to-Clear bits
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*
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* Reads and Writes will be filtered by specified behavior. All other bits not
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* declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
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* "Reserved register fields must be read only and must return 0 (all 0's for
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* multi-bit fields) when read".
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*/
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struct pci_bridge_reg_behavior {
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/* Read-only bits */
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u32 ro;
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@ -33,9 +44,6 @@ struct pci_bridge_reg_behavior {
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/* Write-1-to-clear bits */
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u32 w1c;
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/* Reserved bits (hardwired to 0) */
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u32 rsvd;
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};
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static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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@ -49,7 +57,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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PCI_COMMAND_FAST_BACK) |
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(PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
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.rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
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.w1c = PCI_STATUS_ERROR_BITS << 16,
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},
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[PCI_CLASS_REVISION / 4] = { .ro = ~0 },
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@ -96,8 +103,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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GENMASK(11, 8) | GENMASK(3, 0)),
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.w1c = PCI_STATUS_ERROR_BITS << 16,
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.rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
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},
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[PCI_MEMORY_BASE / 4] = {
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@ -130,12 +135,10 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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[PCI_CAPABILITY_LIST / 4] = {
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.ro = GENMASK(7, 0),
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.rsvd = GENMASK(31, 8),
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},
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[PCI_ROM_ADDRESS1 / 4] = {
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.rw = GENMASK(31, 11) | BIT(0),
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.rsvd = GENMASK(10, 1),
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},
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/*
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@ -158,8 +161,6 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
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.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
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.w1c = BIT(10) << 16,
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.rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
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},
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};
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@ -186,13 +187,11 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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*/
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.w1c = (BIT(6) | GENMASK(3, 0)) << 16,
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.ro = GENMASK(5, 4) << 16,
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.rsvd = GENMASK(15, 7) << 16,
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},
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[PCI_EXP_LNKCAP / 4] = {
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/* All bits are RO, except bit 23 which is reserved */
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.ro = lower_32_bits(~BIT(23)),
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.rsvd = BIT(23),
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},
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[PCI_EXP_LNKCTL / 4] = {
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@ -206,7 +205,6 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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.rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
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.ro = GENMASK(13, 0) << 16,
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.w1c = GENMASK(15, 14) << 16,
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.rsvd = GENMASK(13, 12) | BIT(2),
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},
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[PCI_EXP_SLTCAP / 4] = {
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@ -227,7 +225,6 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
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.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
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PCI_EXP_SLTSTA_EIS) << 16,
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.rsvd = GENMASK(15) | (GENMASK(15, 9) << 16),
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},
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[PCI_EXP_RTCTL / 4] = {
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@ -241,7 +238,6 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
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PCI_EXP_RTCTL_CRSSVE),
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.ro = PCI_EXP_RTCAP_CRSVIS << 16,
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.rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
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},
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[PCI_EXP_RTSTA / 4] = {
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@ -251,7 +247,6 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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*/
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.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
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.w1c = PCI_EXP_RTSTA_PME,
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.rsvd = GENMASK(31, 18),
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},
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};
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@ -359,7 +354,8 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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* Make sure we never return any reserved bit with a value
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* different from 0.
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*/
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*value &= ~behavior[reg / 4].rsvd;
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*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
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behavior[reg / 4].w1c;
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if (size == 1)
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*value = (*value >> (8 * (where & 3))) & 0xff;
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