MIPS: Loongson-3: Fix BRIDGE irq delivery problem
[ Upstream commit360fe725f8
] After commite509bd7da1
("genirq: Allow migration of chained interrupts by installing default action") Loongson-3 fails at here: setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); This is because both chained_action and cascade_irqaction don't have IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET timer interrupt can't be delivered during S3. So we set the irqchip of the chained irq to loongson_irq_chip which doesn't disable the chained irq in CP0.Status. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20434/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -10,7 +10,7 @@
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#define MIPS_CPU_IRQ_BASE 56
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#define MIPS_CPU_IRQ_BASE 56
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#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
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#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
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#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
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#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
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#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
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#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
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#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
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#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
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@ -96,12 +96,6 @@ void mach_irq_dispatch(unsigned int pending)
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}
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}
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}
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}
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.flags = IRQF_NO_SUSPEND,
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.name = "cascade",
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};
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static inline void mask_loongson_irq(struct irq_data *d) { }
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static inline void mask_loongson_irq(struct irq_data *d) { }
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static inline void unmask_loongson_irq(struct irq_data *d) { }
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static inline void unmask_loongson_irq(struct irq_data *d) { }
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@ -147,11 +141,10 @@ void __init mach_init_irq(void)
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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&loongson_irq_chip, handle_percpu_irq);
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irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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/* setup HT1 irq */
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set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
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setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
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set_c0_status(STATUSF_IP2 | STATUSF_IP6);
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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#ifdef CONFIG_HOTPLUG_CPU
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