ixgb: trivial fix space after for
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Jesse Brandeburg
Jeff Garzik
Родитель
52035bdbe8
Коммит
1459336da4
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@ -152,7 +152,7 @@ ixgb_shift_in_bits(struct ixgb_hw *hw)
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eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
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data = 0;
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for(i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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data = data << 1;
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ixgb_raise_clock(hw, &eecd_reg);
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@ -297,7 +297,7 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
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* signal that the command has been completed by raising the DO signal.
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* If DO does not go high in 10 milliseconds, then error out.
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*/
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for(i = 0; i < 200; i++) {
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for (i = 0; i < 200; i++) {
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eecd_reg = IXGB_READ_REG(hw, EECD);
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if (eecd_reg & IXGB_EECD_DO)
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@ -328,7 +328,7 @@ ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
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u16 checksum = 0;
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u16 i;
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for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
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for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
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checksum += ixgb_read_eeprom(hw, i);
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if (checksum == (u16) EEPROM_SUM)
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@ -351,7 +351,7 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
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u16 checksum = 0;
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u16 i;
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for(i = 0; i < EEPROM_CHECKSUM_REG; i++)
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for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
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checksum += ixgb_read_eeprom(hw, i);
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checksum = (u16) EEPROM_SUM - checksum;
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@ -472,7 +472,7 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
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ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
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DEBUGOUT("ixgb_ee: Reading eeprom data\n");
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for(i = 0; i < IXGB_EEPROM_SIZE ; i++) {
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for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
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u16 ee_data;
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ee_data = ixgb_read_eeprom(hw, i);
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checksum += ee_data;
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@ -301,7 +301,7 @@ ixgb_get_regs(struct net_device *netdev,
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*reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */
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/* there are 16 RAR entries in hardware, we only use 3 */
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for(i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) {
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for (i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) {
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*reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */
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*reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */
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}
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@ -441,12 +441,10 @@ ixgb_get_eeprom(struct net_device *netdev,
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return -ENOMEM;
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/* note the eeprom was good because the driver loaded */
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for(i = 0; i <= (last_word - first_word); i++) {
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for (i = 0; i <= (last_word - first_word); i++)
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eeprom_buff[i] = ixgb_get_eeprom_word(hw, (first_word + i));
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}
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memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
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eeprom->len);
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memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
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kfree(eeprom_buff);
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geeprom_error:
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@ -500,7 +498,7 @@ ixgb_set_eeprom(struct net_device *netdev,
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}
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memcpy(ptr, bytes, eeprom->len);
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for(i = 0; i <= (last_word - first_word); i++)
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for (i = 0; i <= (last_word - first_word); i++)
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ixgb_write_eeprom(hw, first_word + i, eeprom_buff[i]);
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/* Update the checksum over the first part of the EEPROM if needed */
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@ -666,7 +664,7 @@ ixgb_get_ethtool_stats(struct net_device *netdev,
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int i;
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ixgb_update_stats(adapter);
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for(i = 0; i < IXGB_STATS_LEN; i++) {
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for (i = 0; i < IXGB_STATS_LEN; i++) {
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char *p = (char *)adapter+ixgb_gstrings_stats[i].stat_offset;
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data[i] = (ixgb_gstrings_stats[i].sizeof_stat ==
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sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
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@ -680,7 +678,7 @@ ixgb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
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switch(stringset) {
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case ETH_SS_STATS:
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for(i=0; i < IXGB_STATS_LEN; i++) {
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for (i = 0; i < IXGB_STATS_LEN; i++) {
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memcpy(data + i * ETH_GSTRING_LEN,
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ixgb_gstrings_stats[i].stat_string,
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ETH_GSTRING_LEN);
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@ -347,7 +347,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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/* Zero out the VLAN Filter Table Array */
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@ -413,7 +413,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
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/* Zero out the other 15 receive addresses. */
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DEBUGOUT("Clearing RAR[1-15]\n");
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for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
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for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
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/* Write high reg first to disable the AV bit first */
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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@ -452,19 +452,18 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
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/* Clear RAR[1-15] */
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DEBUGOUT(" Clearing RAR[1-15]\n");
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for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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}
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/* Clear the MTA */
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DEBUGOUT(" Clearing MTA\n");
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for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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}
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/* Add the new addresses */
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for(i = 0; i < mc_addr_count; i++) {
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for (i = 0; i < mc_addr_count; i++) {
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DEBUGOUT(" Adding the multicast addresses:\n");
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DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
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mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
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@ -649,7 +648,7 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
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{
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u32 offset;
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for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
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return;
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}
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@ -790,7 +789,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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for(i = 0; i < 10; i++)
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for (i = 0; i < 10; i++)
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{
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udelay(10);
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@ -817,7 +816,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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for(i = 0; i < 10; i++)
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for (i = 0; i < 10; i++)
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{
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udelay(10);
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@ -886,7 +885,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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for(i = 0; i < 10; i++)
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for (i = 0; i < 10; i++)
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{
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udelay(10);
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@ -913,7 +912,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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for(i = 0; i < 10; i++)
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for (i = 0; i < 10; i++)
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{
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udelay(10);
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@ -398,7 +398,7 @@ ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto err_ioremap;
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}
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for(i = BAR_1; i <= BAR_5; i++) {
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for (i = BAR_1; i <= BAR_5; i++) {
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if (pci_resource_len(pdev, i) == 0)
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continue;
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if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
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@ -923,7 +923,7 @@ ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
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/* Free all the Tx ring sk_buffs */
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for(i = 0; i < tx_ring->count; i++) {
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for (i = 0; i < tx_ring->count; i++) {
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buffer_info = &tx_ring->buffer_info[i];
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ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
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}
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@ -981,7 +981,7 @@ ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
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/* Free all the Rx ring sk_buffs */
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for(i = 0; i < rx_ring->count; i++) {
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for (i = 0; i < rx_ring->count; i++) {
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buffer_info = &rx_ring->buffer_info[i];
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if (buffer_info->skb) {
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@ -1298,7 +1298,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
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if (++i == tx_ring->count) i = 0;
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}
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for(f = 0; f < nr_frags; f++) {
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for (f = 0; f < nr_frags; f++) {
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struct skb_frag_struct *frag;
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frag = &skb_shinfo(skb)->frags[f];
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@ -1727,7 +1727,7 @@ ixgb_intr(int irq, void *data)
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* every pass through this for loop checks both receive and
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* transmit queues for completed descriptors, intended to
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* avoid starvation issues and assist tx/rx fairness. */
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for(i = 0; i < IXGB_MAX_INTR; i++)
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for (i = 0; i < IXGB_MAX_INTR; i++)
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if (!ixgb_clean_rx_irq(adapter) &
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!ixgb_clean_tx_irq(adapter))
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break;
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@ -2196,7 +2196,7 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
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if (adapter->vlgrp) {
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u16 vid;
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for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
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for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
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if (!vlan_group_get_device(adapter->vlgrp, vid))
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continue;
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ixgb_vlan_rx_add_vid(adapter->netdev, vid);
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@ -226,7 +226,7 @@ ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt)
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int i;
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struct ixgb_opt_list *ent;
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for(i = 0; i < opt->arg.l.nr; i++) {
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for (i = 0; i < opt->arg.l.nr; i++) {
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ent = &opt->arg.l.p[i];
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if (*value == ent->i) {
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if (ent->str[0] != '\0')
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