Merge branch 'remotes/lorenzo/pci/misc'
- Add macros for PCI Configuration Mechanism #1 and use them in the ftpci100, mt7621, and tegra drivers (Pali Rohár) * remotes/lorenzo/pci/misc: PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macro PCI: ftpci100: Use PCI_CONF1_ADDRESS() macro PCI: Add standard PCI Config Address macros
This commit is contained in:
Bjorn Helgaas
Коммит
14868d783c
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@ -103,13 +103,6 @@
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#define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
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#define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
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/* Defines for PCI configuration command register */
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#define PCI_CONF_ENABLE BIT(31)
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#define PCI_CONF_WHERE(r) ((r) & 0xFC)
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#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
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#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
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#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
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/**
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* struct faraday_pci_variant - encodes IP block differences
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* @cascaded_irq: this host has cascaded IRQs from an interrupt controller
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@ -190,11 +183,8 @@ static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
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unsigned int fn, int config, int size,
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u32 *value)
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{
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writel(PCI_CONF_BUS(bus_number) |
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PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn),
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PCI_FUNC(fn), config),
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p->base + FTPCI_CONFIG);
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*value = readl(p->base + FTPCI_DATA);
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@ -225,11 +215,8 @@ static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
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{
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int ret = PCIBIOS_SUCCESSFUL;
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writel(PCI_CONF_BUS(bus_number) |
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PCI_CONF_DEVICE(PCI_SLOT(fn)) |
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn),
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PCI_FUNC(fn), config),
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p->base + FTPCI_CONFIG);
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switch (size) {
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@ -415,13 +415,6 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
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* address (access to which generates correct config transaction) falls in
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* this 4 KiB region.
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*/
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static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
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unsigned int where)
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{
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return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
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(PCI_FUNC(devfn) << 8) | (where & 0xff);
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}
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static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn,
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int where)
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@ -443,7 +436,9 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
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unsigned int offset;
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u32 base;
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offset = tegra_pcie_conf_offset(bus->number, devfn, where);
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offset = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where) &
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~PCI_CONF1_ENABLE;
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/* move 4 KiB window to offset within the FPCI region */
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base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
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@ -30,6 +30,8 @@
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#include <linux/reset.h>
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#include <linux/sys_soc.h>
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#include "../pci.h"
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/* MediaTek-specific configuration registers */
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#define PCIE_FTS_NUM 0x70c
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#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
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@ -120,19 +122,12 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
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writel_relaxed(val, port->base + reg);
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}
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static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
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(func << 8) | (where & 0xfc) | 0x80000000;
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}
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static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct mt7621_pcie *pcie = bus->sysdata;
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u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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@ -147,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops = {
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static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
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{
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u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
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u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
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@ -156,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
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static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
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u32 reg, u32 val)
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{
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u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
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u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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@ -776,4 +776,49 @@ static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
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}
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#endif
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/*
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* Config Address for PCI Configuration Mechanism #1
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*
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* See PCI Local Bus Specification, Revision 3.0,
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* Section 3.2.2.3.2, Figure 3-2, p. 50.
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*/
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#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
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#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
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#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
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#define PCI_CONF1_BUS_MASK 0xff
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#define PCI_CONF1_DEV_MASK 0x1f
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#define PCI_CONF1_FUNC_MASK 0x7
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#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
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#define PCI_CONF1_ENABLE BIT(31)
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#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
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#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
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#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
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#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
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#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
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(PCI_CONF1_ENABLE | \
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PCI_CONF1_BUS(bus) | \
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PCI_CONF1_DEV(dev) | \
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PCI_CONF1_FUNC(func) | \
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PCI_CONF1_REG(reg))
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/*
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* Extension of PCI Config Address for accessing extended PCIe registers
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*
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* No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
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* or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
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* are used for specifying additional 4 high bits of PCI Express register.
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*/
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#define PCI_CONF1_EXT_REG_SHIFT 16
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#define PCI_CONF1_EXT_REG_MASK 0xf00
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#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
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#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
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(PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
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PCI_CONF1_EXT_REG(reg))
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#endif /* DRIVERS_PCI_H */
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