edac: i5400 fix csrow mapping
The i5400 EDAC driver has several bugs with chip-select row computation which most likely lead to bugs in detailed error reporting. Attempts to contact the authors have gone mostly unanswered so I am presenting my diff here. I do not subscribe to lkml and would appreciate being kept in the cc. The most egregious problem was miscalculating the addresses of MTR registers after register 0 by assuming they are 32bit rather than 16. This caused the driver to miss half of the memories. Most motherboards tend to have only 8 dimm slots and not 16, so this may not have been noticed before. Further, the row calculations multiplied the number of dimms several times, ultimately ending up with a maximum row of 32. The chipset only supports 4 dimms in each of 4 channels, so csrow could not be higher than 4 unless you use a row per-rank with dual-rank dimms. I opted to eliminate this behavior as it is confusing to the user and the error reporting works by slot and not rank. This gives a much clearer view of memory by slot and channel in /sys. Signed-off-by: Jeff Roberson <jroberson@jroberson.net> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Jeff Roberson
Linus Torvalds
Родитель
8c85dd8730
Коммит
156edd4aaa
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@ -46,9 +46,10 @@
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/* Limits for i5400 */
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#define NUM_MTRS_PER_BRANCH 4
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#define CHANNELS_PER_BRANCH 2
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#define MAX_DIMMS_PER_CHANNEL NUM_MTRS_PER_BRANCH
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#define MAX_CHANNELS 4
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#define MAX_DIMMS (MAX_CHANNELS * 4) /* Up to 4 DIMM's per channel */
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#define MAX_CSROWS (MAX_DIMMS * 2) /* max possible csrows per channel */
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/* max possible csrows per channel */
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#define MAX_CSROWS (MAX_DIMMS_PER_CHANNEL)
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/* Device 16,
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* Function 0: System Address
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@ -331,7 +332,6 @@ static const struct i5400_dev_info i5400_devs[] = {
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struct i5400_dimm_info {
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int megabytes; /* size, 0 means not present */
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int dual_rank;
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};
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/* driver private data structure */
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@ -849,11 +849,9 @@ static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
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int n;
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/* There is one MTR for each slot pair of FB-DIMMs,
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Each slot may have one or two ranks (2 csrows),
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Each slot pair may be at branch 0 or branch 1.
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So, csrow should be divided by eight
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*/
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n = csrow >> 3;
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n = csrow;
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if (n >= NUM_MTRS_PER_BRANCH) {
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debugf0("ERROR: trying to access an invalid csrow: %d\n",
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@ -905,25 +903,22 @@ static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
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amb_present_reg = determine_amb_present_reg(pvt, channel);
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/* Determine if there is a DIMM present in this DIMM slot */
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if (amb_present_reg & (1 << (csrow >> 1))) {
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dinfo->dual_rank = MTR_DIMM_RANK(mtr);
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if (amb_present_reg & (1 << csrow)) {
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/* Start with the number of bits for a Bank
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* on the DRAM */
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addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
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/* Add thenumber of ROW bits */
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addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
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/* add the number of COLUMN bits */
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addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
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/* add the number of RANK bits */
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addrBits += MTR_DIMM_RANK(mtr);
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if (!((dinfo->dual_rank == 0) &&
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((csrow & 0x1) == 0x1))) {
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/* Start with the number of bits for a Bank
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* on the DRAM */
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addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
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/* Add thenumber of ROW bits */
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addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
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/* add the number of COLUMN bits */
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addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
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addrBits += 6; /* add 64 bits per DIMM */
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addrBits -= 20; /* divide by 2^^20 */
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addrBits -= 3; /* 8 bits per bytes */
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addrBits += 6; /* add 64 bits per DIMM */
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addrBits -= 20; /* divide by 2^^20 */
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addrBits -= 3; /* 8 bits per bytes */
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dinfo->megabytes = 1 << addrBits;
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}
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dinfo->megabytes = 1 << addrBits;
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}
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}
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}
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@ -951,12 +946,12 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
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return;
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}
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/* Scan all the actual CSROWS (which is # of DIMMS * 2)
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/* Scan all the actual CSROWS
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* and calculate the information for each DIMM
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* Start with the highest csrow first, to display it first
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* and work toward the 0th csrow
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*/
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max_csrows = pvt->maxdimmperch * 2;
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max_csrows = pvt->maxdimmperch;
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for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
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/* on an odd csrow, first output a 'boundary' marker,
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@ -1064,7 +1059,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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/* Get the set of MTR[0-3] regs by each branch */
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for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++) {
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int where = MTR0 + (slot_row * sizeof(u32));
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int where = MTR0 + (slot_row * sizeof(u16));
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/* Branch 0 set of MTR registers */
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pci_read_config_word(pvt->branch_0, where,
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@ -1146,7 +1141,7 @@ static int i5400_init_csrows(struct mem_ctl_info *mci)
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pvt = mci->pvt_info;
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channel_count = pvt->maxch;
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max_csrows = pvt->maxdimmperch * 2;
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max_csrows = pvt->maxdimmperch;
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empty = 1; /* Assume NO memory */
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@ -1214,28 +1209,6 @@ static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
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fbd_error_mask);
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}
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/*
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* i5400_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
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*
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* ask the device how many channels are present and how many CSROWS
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* as well
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*/
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static void i5400_get_dimm_and_channel_counts(struct pci_dev *pdev,
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int *num_dimms_per_channel,
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int *num_channels)
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{
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u8 value;
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/* Need to retrieve just how many channels and dimms per channel are
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* supported on this memory controller
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*/
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pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
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*num_dimms_per_channel = (int)value * 2;
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pci_read_config_byte(pdev, MAXCH, &value);
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*num_channels = (int)value;
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}
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/*
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* i5400_probe1 Probe for ONE instance of device to see if it is
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* present.
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@ -1263,22 +1236,16 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
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if (PCI_FUNC(pdev->devfn) != 0)
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return -ENODEV;
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/* Ask the devices for the number of CSROWS and CHANNELS so
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* that we can calculate the memory resources, etc
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*
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* The Chipset will report what it can handle which will be greater
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* or equal to what the motherboard manufacturer will implement.
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*
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* As we don't have a motherboard identification routine to determine
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/* As we don't have a motherboard identification routine to determine
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* actual number of slots/dimms per channel, we thus utilize the
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* resource as specified by the chipset. Thus, we might have
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* have more DIMMs per channel than actually on the mobo, but this
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* allows the driver to support upto the chipset max, without
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* some fancy mobo determination.
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*/
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i5400_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
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&num_channels);
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num_csrows = num_dimms_per_channel * 2;
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num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
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num_channels = MAX_CHANNELS;
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num_csrows = num_dimms_per_channel;
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debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
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__func__, num_channels, num_dimms_per_channel, num_csrows);
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