pinctrl: aspeed-g6: Add AST2600 pinconf support
The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Johnny Huang
Linus Walleij
Родитель
5f52c85384
Коммит
15711ba6ff
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@ -28,6 +28,8 @@
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#define SCU438 0x438 /* Multi-function Pin Control #10 */
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#define SCU440 0x440 /* USB Multi-function Pin Control #12 */
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#define SCU450 0x450 /* Multi-function Pin Control #14 */
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#define SCU454 0x454 /* Multi-function Pin Control #15 */
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#define SCU458 0x458 /* Multi-function Pin Control #16 */
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#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
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#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
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#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
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@ -36,6 +38,13 @@
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#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
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#define SCU500 0x500 /* Hardware Strap 1 */
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#define SCU510 0x510 /* Hardware Strap 2 */
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#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
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#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
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#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
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#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
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#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */
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#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
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#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
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#define SCU694 0x694 /* Multi-function Pin Control #25 */
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#define SCUC20 0xC20 /* PCIE configuration Setting Control */
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@ -2333,6 +2342,260 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
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ASPEED_PINCTRL_FUNC(WDTRST4),
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};
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static struct aspeed_pin_config aspeed_g6_configs[] = {
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/* GPIOB7 */
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ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
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/* GPIOB6 */
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ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
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/* GPIOB5 */
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ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
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/* GPIOB4 */
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ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
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/* GPIOB3 */
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ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
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/* GPIOB2 */
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ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
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/* GPIOB1 */
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ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
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/* GPIOB0 */
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ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
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/* GPIOH3 */
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ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
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/* GPIOH2 */
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ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
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/* GPIOH1 */
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ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
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/* GPIOH0 */
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ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
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/* GPIOL7 */
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ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
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/* GPIOL6 */
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ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
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/* GPIOL5 */
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ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
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/* GPIOL4 */
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ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
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/* GPIOJ7 */
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ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
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/* GPIOJ6 */
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ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
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/* GPIOJ5 */
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ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
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/* GPIOJ4 */
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ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
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/* GPIOJ3 */
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ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
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/* GPIOJ2 */
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ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
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/* GPIOJ1 */
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ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
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/* GPIOJ0 */
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ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
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/* GPIOI7 */
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ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
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/* GPIOI6 */
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ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
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/* GPIOI5 */
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ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
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/* GPIOI4 */
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ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
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/* GPIOI3 */
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ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
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/* GPIOI2 */
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ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
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/* GPIOI1 */
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ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
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/* GPIOI0 */
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ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
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/* GPIOP7 */
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ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
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/* GPIOP6 */
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ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
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/* GPIOP5 */
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ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
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/* GPIOP4 */
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ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
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/* GPIOP3 */
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ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
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/* GPIOP2 */
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ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
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/* GPIOP1 */
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ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
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/* GPIOP0 */
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ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
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/* GPIOO7 */
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ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
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/* GPIOO6 */
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ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
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/* GPIOO5 */
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ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
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/* GPIOO4 */
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ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
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/* GPIOO3 */
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ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
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/* GPIOO2 */
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ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
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/* GPIOO1 */
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ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
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/* GPIOO0 */
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ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
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/* GPION7 */
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ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
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/* GPION6 */
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ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
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/* GPION5 */
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ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
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/* GPION4 */
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ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
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/* GPION3 */
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ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
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/* GPION2 */
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ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
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/* GPION1 */
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ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
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/* GPION0 */
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ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
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/* GPIOM7 */
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ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
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/* GPIOM6 */
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ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
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/* GPIOM5 */
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ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
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/* GPIOM4 */
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ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
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/* GPIOM3 */
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ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
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/* GPIOM2 */
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ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
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/* GPIOM1 */
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ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
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/* GPIOM0 */
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ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
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/* GPIOS7 */
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ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23),
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/* GPIOS6 */
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ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22),
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/* GPIOS5 */
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ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21),
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/* GPIOS4 */
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ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20),
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/* GPIOS3*/
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ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19),
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/* GPIOS2 */
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ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18),
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/* GPIOS1 */
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ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17),
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/* GPIOS0 */
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ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16),
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/* GPIOR7 */
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ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15),
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/* GPIOR6 */
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ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14),
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/* GPIOR5 */
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ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13),
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/* GPIOR4 */
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ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12),
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/* GPIOR3*/
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ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11),
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/* GPIOR2 */
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ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10),
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/* GPIOR1 */
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ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9),
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/* GPIOR0 */
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ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8),
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/* GPIOX7 */
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ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
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/* GPIOX6 */
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ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
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/* GPIOX5 */
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ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
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/* GPIOX4 */
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ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
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/* GPIOX3*/
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ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
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/* GPIOX2 */
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ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
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/* GPIOX1 */
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ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
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/* GPIOX0 */
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ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
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/* GPIOV7 */
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ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
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/* GPIOV6 */
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ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
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/* GPIOV5 */
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ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
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/* GPIOV4 */
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ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
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/* GPIOV3*/
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ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
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/* GPIOV2 */
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ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
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/* GPIOV1 */
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ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
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/* GPIOV0 */
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ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
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/* GPIOZ7 */
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ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
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/* GPIOZ6 */
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ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
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/* GPIOZ5 */
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ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
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/* GPIOZ4 */
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ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
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/* GPIOZ3*/
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ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
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/* GPIOZ1 */
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ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
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/* GPIOZ0 */
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ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
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/* GPIOY6 */
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ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
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/* GPIOY5 */
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ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
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/* GPIOY4 */
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ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
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/* GPIOY3 */
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ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
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/* GPIOY2 */
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ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
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/* GPIOY1 */
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ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
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/* GPIOY0 */
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ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
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/* LAD3 */
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{ PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
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/* LAD2 */
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{ PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
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/* LAD1 */
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{ PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
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/* LAD0 */
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{ PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
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/* MAC3 */
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{ PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
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{ PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
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/* MAC4 */
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{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
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{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
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};
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/**
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* Configure a pin's signal by applying an expression's descriptor state for
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* all descriptors in the expression.
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@ -2400,6 +2663,20 @@ static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
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return 0;
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}
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static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
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{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
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{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
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{ PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
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{ PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
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{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
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{ PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
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{ PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
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{ PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
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{ PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
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{ PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
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{ PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
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};
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static const struct aspeed_pinmux_ops aspeed_g5_ops = {
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.set = aspeed_g6_sig_expr_set,
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};
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@ -2414,6 +2691,10 @@ static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
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.functions = aspeed_g6_functions,
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.nfunctions = ARRAY_SIZE(aspeed_g6_functions),
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},
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.configs = aspeed_g6_configs,
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.nconfigs = ARRAY_SIZE(aspeed_g6_configs),
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.confmaps = aspeed_g6_pin_config_map,
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.nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
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};
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static const struct pinmux_ops aspeed_g6_pinmux_ops = {
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@ -2434,12 +2715,21 @@ static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
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.dt_free_map = pinctrl_utils_free_map,
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};
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static const struct pinconf_ops aspeed_g6_conf_ops = {
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.is_generic = true,
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.pin_config_get = aspeed_pin_config_get,
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.pin_config_set = aspeed_pin_config_set,
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.pin_config_group_get = aspeed_pin_config_group_get,
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.pin_config_group_set = aspeed_pin_config_group_set,
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};
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static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
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.name = "aspeed-g6-pinctrl",
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.pins = aspeed_g6_pins,
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.npins = ARRAY_SIZE(aspeed_g6_pins),
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.pctlops = &aspeed_g6_pinctrl_ops,
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.pmxops = &aspeed_g6_pinmux_ops,
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.confops = &aspeed_g6_conf_ops,
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};
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static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
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@ -41,6 +41,13 @@ struct aspeed_pin_config {
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.mask = BIT_MASK(bit_) \
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}
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#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
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#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
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/*
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* Aspeed pin configuration description.
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*
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