MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20. 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1000-Neo. 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1830-Neo. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780 Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie)
Thomas Bogendoerfer
Родитель
7701f264a7
Коммит
158c774d3c
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@ -69,9 +69,11 @@
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eth0_power: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "eth0_power";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
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enable-active-high;
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};
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@ -83,16 +85,39 @@
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wlan0_power: fixedregulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "wlan0_power";
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gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
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enable-active-high;
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};
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otg_power: fixedregulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "otg_power";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
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enable-active-high;
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};
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};
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&ext {
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clock-frequency = <48000000>;
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};
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&cgu {
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/*
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* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
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* precision.
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*/
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assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
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assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
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assigned-clock-rates = <48000000>;
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};
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&mmc0 {
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status = "okay";
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@ -396,6 +421,16 @@
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status = "okay";
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};
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&otg_phy {
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status = "okay";
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vcc-supply = <&otg_power>;
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};
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&otg {
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status = "okay";
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};
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&pinctrl {
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pins_uart0: uart0 {
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function = "uart0";
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@ -489,7 +524,11 @@
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};
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&tcu {
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/* 3 MHz for the system timer and clocksource */
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assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
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assigned-clock-rates = <3000000>, <3000000>;
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/*
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* 750 kHz for the system timer and 3 MHz for the clocksource,
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* use channel #0 for the system timer, #1 for the clocksource.
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*/
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assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
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<&tcu TCU_CLK_OST>;
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assigned-clock-rates = <750000>, <3000000>, <3000000>;
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};
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@ -3,7 +3,7 @@
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#include "x1000.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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#include <dt-bindings/clock/ingenic,sysost.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -31,6 +31,42 @@
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};
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};
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ssi: spi-gpio {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <1>;
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mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
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miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
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sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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spi-max-frequency = <50000000>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpc>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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wlan_pwrseq: msc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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@ -43,13 +79,19 @@
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clock-frequency = <24000000>;
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};
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&tcu {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
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assigned-clock-rates = <1500000>, <1500000>;
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&cgu {
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/*
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* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
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* precision.
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*/
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assigned-clocks = <&cgu X1000_CLK_RTC>;
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assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
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};
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/* Use channel #0 for the system timer channel #2 for the clocksource */
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ingenic,pwm-channels-mask = <0xfa>;
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&ost {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clock-rates = <1500000>, <1500000>;
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};
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&uart2 {
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@ -135,6 +177,14 @@
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};
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};
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&otg_phy {
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status = "okay";
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};
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&otg {
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status = "okay";
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};
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&pinctrl {
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pins_uart2: uart2 {
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function = "uart2";
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@ -3,7 +3,7 @@
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#include "x1830.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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#include <dt-bindings/clock/ingenic,sysost.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -31,6 +31,42 @@
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};
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};
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ssi0: spi-gpio {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <1>;
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mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
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miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
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sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
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status = "okay";
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spi-max-frequency = <50000000>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpb>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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wlan_pwrseq: msc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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@ -43,13 +79,19 @@
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clock-frequency = <24000000>;
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};
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&tcu {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
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assigned-clock-rates = <1500000>, <1500000>;
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&cgu {
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/*
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* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
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* precision.
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*/
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assigned-clocks = <&cgu X1830_CLK_RTC>;
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assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
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};
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/* Use channel #0 for the system timer channel #2 for the clocksource */
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ingenic,pwm-channels-mask = <0xfa>;
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&ost {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clock-rates = <1500000>, <1500000>;
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};
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&uart1 {
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@ -73,6 +115,10 @@
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};
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};
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&dtrng {
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status = "okay";
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};
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&msc0 {
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status = "okay";
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@ -135,6 +181,14 @@
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};
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};
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&otg_phy {
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status = "okay";
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};
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&otg {
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status = "okay";
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};
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&pinctrl {
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pins_uart1: uart1 {
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function = "uart1";
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@ -61,13 +61,34 @@
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};
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cgu: jz4780-cgu@10000000 {
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compatible = "ingenic,jz4780-cgu";
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compatible = "ingenic,jz4780-cgu", "simple-mfd";
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reg = <0x10000000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10000000 0x100>;
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#clock-cells = <1>;
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clocks = <&ext>, <&rtc>;
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clock-names = "ext", "rtc";
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#clock-cells = <1>;
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otg_phy: usb-phy@3c {
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compatible = "ingenic,jz4780-phy";
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reg = <0x3c 0x10>;
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clocks = <&cgu JZ4780_CLK_OTG1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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rng: rng@d8 {
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compatible = "ingenic,jz4780-rng";
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reg = <0xd8 0x8>;
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status = "disabled";
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};
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};
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tcu: timer@10002000 {
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@ -494,4 +515,24 @@
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status = "disabled";
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};
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otg: usb@13500000 {
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compatible = "ingenic,jz4780-otg", "snps,dwc2";
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reg = <0x13500000 0x40000>;
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interrupt-parent = <&intc>;
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interrupts = <21>;
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clocks = <&cgu JZ4780_CLK_UHC>;
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clock-names = "otg";
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phys = <&otg_phy>;
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phy-names = "usb2-phy";
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g-rx-fifo-size = <768>;
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g-np-tx-fifo-size = <256>;
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g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
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status = "disabled";
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};
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};
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@ -52,13 +52,47 @@
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};
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cgu: x1000-cgu@10000000 {
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compatible = "ingenic,x1000-cgu";
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compatible = "ingenic,x1000-cgu", "simple-mfd";
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reg = <0x10000000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x10000000 0x100>;
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#clock-cells = <1>;
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clocks = <&exclk>, <&rtclk>;
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clock-names = "ext", "rtc";
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otg_phy: usb-phy@3c {
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compatible = "ingenic,x1000-phy";
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reg = <0x3c 0x10>;
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clocks = <&cgu X1000_CLK_OTGPHY>;
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#phy-cells = <0>;
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status = "disabled";
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};
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rng: rng@d8 {
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compatible = "ingenic,x1000-rng";
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reg = <0xd8 0x8>;
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status = "disabled";
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};
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};
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ost: timer@12000000 {
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compatible = "ingenic,x1000-ost";
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reg = <0x12000000 0x3c>;
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#clock-cells = <1>;
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clocks = <&cgu X1000_CLK_OST>;
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clock-names = "ost";
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interrupt-parent = <&cpuintc>;
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interrupts = <3>;
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};
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tcu: timer@10002000 {
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@ -323,4 +357,24 @@
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status = "disabled";
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};
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};
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otg: usb@13500000 {
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compatible = "ingenic,x1000-otg", "snps,dwc2";
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reg = <0x13500000 0x40000>;
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interrupt-parent = <&intc>;
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interrupts = <21>;
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clocks = <&cgu X1000_CLK_OTG>;
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clock-names = "otg";
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phys = <&otg_phy>;
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phy-names = "usb2-phy";
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g-rx-fifo-size = <768>;
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g-np-tx-fifo-size = <256>;
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g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
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status = "disabled";
|
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};
|
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};
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@ -52,13 +52,40 @@
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|||
};
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||||
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||||
cgu: x1830-cgu@10000000 {
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||||
compatible = "ingenic,x1830-cgu";
|
||||
compatible = "ingenic,x1830-cgu", "simple-mfd";
|
||||
reg = <0x10000000 0x100>;
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||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
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ranges = <0x0 0x10000000 0x100>;
|
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|
||||
#clock-cells = <1>;
|
||||
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||||
clocks = <&exclk>, <&rtclk>;
|
||||
clock-names = "ext", "rtc";
|
||||
|
||||
otg_phy: usb-phy@3c {
|
||||
compatible = "ingenic,x1830-phy";
|
||||
reg = <0x3c 0x10>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_OTGPHY>;
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ost: timer@12000000 {
|
||||
compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
|
||||
reg = <0x12000000 0x3c>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_OST>;
|
||||
clock-names = "ost";
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
tcu: timer@10002000 {
|
||||
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@ -236,6 +263,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dtrng: trng@10072000 {
|
||||
compatible = "ingenic,x1830-dtrng";
|
||||
reg = <0x10072000 0xc>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_DTRNG>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdma: dma-controller@13420000 {
|
||||
compatible = "ingenic,x1830-dma";
|
||||
reg = <0x13420000 0x400
|
||||
|
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@ -311,4 +347,24 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
otg: usb@13500000 {
|
||||
compatible = "ingenic,x1830-otg", "snps,dwc2";
|
||||
reg = <0x13500000 0x40000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <21>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_OTG>;
|
||||
clock-names = "otg";
|
||||
|
||||
phys = <&otg_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
|
||||
g-rx-fifo-size = <768>;
|
||||
g-np-tx-fifo-size = <256>;
|
||||
g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
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