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Orion: general cleanup 

Various Orion cleanups:
- Unify GPL license banner format across all files.
- Unify naming of .h double inclusion guard preprocessor macros.
- Unify spelling of "PCIe" (variants seen: PCIE, PCIe, PCI-EX.)
- Various typo fixes.
- Remove __init attributes from prototypes declared in headers.
- Remove trailing comments from #endif statements.
- Mark a couple of locally-used-only structs static.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek 2008-03-27 14:51:41 -04:00 коммит произвёл Nicolas Pitre
Родитель d50c60a87a
Коммит 159ffb3a04
18 изменённых файлов: 66 добавлений и 63 удалений
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8
arch/arm/mach-orion/addr-map.c
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@ -5,8 +5,8 @@
* *
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
@ -45,9 +45,9 @@
* Generic Address Decode Windows bit settings * Generic Address Decode Windows bit settings
*/ */
#define TARGET_DDR 0 #define TARGET_DDR 0
#define TARGET_DEV_BUS 1
#define TARGET_PCI 3 #define TARGET_PCI 3
#define TARGET_PCIE 4 #define TARGET_PCIE 4
#define TARGET_DEV_BUS 1
#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
((n) == 1) ? 0xd : \ ((n) == 1) ? 0xd : \
((n) == 2) ? 0xb : \ ((n) == 2) ? 0xb : \
@ -64,7 +64,7 @@
#define WIN_EN 1 #define WIN_EN 1
/* /*
* Helpers to get DDR banks info * Helpers to get DDR bank info
*/ */
#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))

6
arch/arm/mach-orion/common.c
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@ -5,8 +5,8 @@
* *
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
@ -363,7 +363,7 @@ void __init orion_init(void)
orion_setup_eth_wins(); orion_setup_eth_wins();
/* /*
* REgister devices * Register devices.
*/ */
platform_device_register(&orion_uart); platform_device_register(&orion_uart);
platform_device_register(&orion_ehci0); platform_device_register(&orion_ehci0);

19
arch/arm/mach-orion/common.h
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@ -1,13 +1,13 @@
#ifndef __ARCH_ORION_COMMON_H__ #ifndef __ARCH_ORION_COMMON_H
#define __ARCH_ORION_COMMON_H__ #define __ARCH_ORION_COMMON_H
/* /*
* Basic Orion init functions used early by machine-setup. * Basic Orion init functions used early by machine-setup.
*/ */
void __init orion_map_io(void); void orion_map_io(void);
void __init orion_init_irq(void); void orion_init_irq(void);
void __init orion_init(void); void orion_init(void);
extern struct sys_timer orion_timer; extern struct sys_timer orion_timer;
/* /*
@ -43,7 +43,7 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
* (/mach-orion/gpio.c). * (/mach-orion/gpio.c).
*/ */
void __init orion_gpio_set_valid_pins(u32 pins); void orion_gpio_set_valid_pins(u32 pins);
void gpio_display(void); /* debug */ void gpio_display(void); /* debug */
/* /*
@ -52,7 +52,7 @@ void gpio_display(void); /* debug */
struct mv643xx_eth_platform_data; struct mv643xx_eth_platform_data;
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); void orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
/* /*
* Orion Sata platform_data, used by machine-setup * Orion Sata platform_data, used by machine-setup
@ -60,7 +60,7 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
struct mv_sata_platform_data; struct mv_sata_platform_data;
void __init orion_sata_init(struct mv_sata_platform_data *sata_data); void orion_sata_init(struct mv_sata_platform_data *sata_data);
struct machine_desc; struct machine_desc;
struct meminfo; struct meminfo;
@ -68,4 +68,5 @@ struct tag;
extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
char **, struct meminfo *); char **, struct meminfo *);
#endif /* __ARCH_ORION_COMMON_H__ */
#endif

4
arch/arm/mach-orion/db88f5281-setup.c
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@ -5,8 +5,8 @@
* *
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

4
arch/arm/mach-orion/gpio.c
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@ -5,8 +5,8 @@
* *
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

2
arch/arm/mach-orion/irq.c
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@ -6,7 +6,7 @@
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

4
arch/arm/mach-orion/kurobox_pro-setup.c
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@ -3,8 +3,8 @@
* *
* Maintainer: Ronen Shitrit <rshitrit@marvell.com> * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

32
arch/arm/mach-orion/pci.c
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@ -1,12 +1,12 @@
/* /*
* arch/arm/mach-orion/pci.c * arch/arm/mach-orion/pci.c
* *
* PCI and PCIE functions for Marvell Orion System On Chip * PCI and PCIe functions for Marvell Orion System On Chip
* *
* Maintainer: Tzachi Perelstein <tzachi@marvell.com> * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
@ -18,12 +18,12 @@
#include "common.h" #include "common.h"
/***************************************************************************** /*****************************************************************************
* Orion has one PCIE controller and one PCI controller. * Orion has one PCIe controller and one PCI controller.
* *
* Note1: The local PCIE bus number is '0'. The local PCI bus number * Note1: The local PCIe bus number is '0'. The local PCI bus number
* follows the scanned PCIE bridged busses, if any. * follows the scanned PCIe bridged busses, if any.
* *
* Note2: It is possible for PCI/PCIE agents to access many subsystem's * Note2: It is possible for PCI/PCIe agents to access many subsystem's
* space, by configuring BARs and Address Decode Windows, e.g. flashes on * space, by configuring BARs and Address Decode Windows, e.g. flashes on
* device bus, Orion registers, etc. However this code only enable the * device bus, Orion registers, etc. However this code only enable the
* access to DDR banks. * access to DDR banks.
@ -31,7 +31,7 @@
/***************************************************************************** /*****************************************************************************
* PCIE controller * PCIe controller
****************************************************************************/ ****************************************************************************/
#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE)
@ -67,7 +67,7 @@ static int pcie_valid_config(int bus, int dev)
/* /*
* PCIE config cycles are done by programming the PCIE_CONF_ADDR register * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
* and then reading the PCIE_CONF_DATA register. Need to make sure these * and then reading the PCIE_CONF_DATA register. Need to make sure these
* transactions are atomic. * transactions are atomic.
*/ */
@ -133,7 +133,7 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return ret; return ret;
} }
struct pci_ops pcie_ops = { static struct pci_ops pcie_ops = {
.read = pcie_rd_conf, .read = pcie_rd_conf,
.write = pcie_wr_conf, .write = pcie_wr_conf,
}; };
@ -170,23 +170,23 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/* /*
* IORESOURCE_IO * IORESOURCE_IO
*/ */
res[0].name = "PCI-EX I/O Space"; res[0].name = "PCIe I/O Space";
res[0].flags = IORESOURCE_IO; res[0].flags = IORESOURCE_IO;
res[0].start = ORION_PCIE_IO_BUS_BASE; res[0].start = ORION_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0])) if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIE IO resource failed\n"); panic("Request PCIe IO resource failed\n");
sys->resource[0] = &res[0]; sys->resource[0] = &res[0];
/* /*
* IORESOURCE_MEM * IORESOURCE_MEM
*/ */
res[1].name = "PCI-EX Memory Space"; res[1].name = "PCIe Memory Space";
res[1].flags = IORESOURCE_MEM; res[1].flags = IORESOURCE_MEM;
res[1].start = ORION_PCIE_MEM_PHYS_BASE; res[1].start = ORION_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1])) if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIE Memory resource failed\n"); panic("Request PCIe Memory resource failed\n");
sys->resource[1] = &res[1]; sys->resource[1] = &res[1];
sys->resource[2] = NULL; sys->resource[2] = NULL;
@ -351,7 +351,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
PCI_FUNC(devfn), where, size, val); PCI_FUNC(devfn), where, size, val);
} }
struct pci_ops pci_ops = { static struct pci_ops pci_ops = {
.read = orion_pci_rd_conf, .read = orion_pci_rd_conf,
.write = orion_pci_wr_conf, .write = orion_pci_wr_conf,
}; };
@ -508,7 +508,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
/***************************************************************************** /*****************************************************************************
* General PCIE + PCI * General PCIe + PCI
****************************************************************************/ ****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev) static void __devinit rc_pci_fixup(struct pci_dev *dev)
{ {

4
arch/arm/mach-orion/rd88f5182-setup.c
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@ -5,8 +5,8 @@
* *
* Maintainer: Ronen Shitrit <rshitrit@marvell.com> * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

2
include/asm-arm/arch-orion/debug-macro.S
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@ -1,5 +1,5 @@
/* /*
* linux/include/asm-arm/arch-orion/debug-macro.S * include/asm-arm/arch-orion/debug-macro.S
* *
* Debugging macro include header * Debugging macro include header
* *

4
include/asm-arm/arch-orion/hardware.h
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@ -6,8 +6,8 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_HARDWARE_H__ #ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H__ #define __ASM_ARCH_HARDWARE_H
#include "orion.h" #include "orion.h"

8
include/asm-arm/arch-orion/io.h
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@ -3,13 +3,13 @@
* *
* Tzachi Perelstein <tzachi@marvell.com> * Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
#ifndef __ASM_ARM_ARCH_IO_H #ifndef __ASM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H #define __ASM_ARCH_IO_H
#include "orion.h" #include "orion.h"

7
include/asm-arm/arch-orion/irqs.h
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@ -10,8 +10,8 @@
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
#ifndef __ASM_ARCH_IRQS_H__ #ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H__ #define __ASM_ARCH_IRQS_H
#include "orion.h" /* need GPIO_MAX */ #include "orion.h" /* need GPIO_MAX */
@ -58,4 +58,5 @@
#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) #define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
#endif /* __ASM_ARCH_IRQS_H__ */
#endif

5
include/asm-arm/arch-orion/memory.h
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@ -4,12 +4,13 @@
* Marvell Orion memory definitions * Marvell Orion memory definitions
*/ */
#ifndef __ASM_ARCH_MMU_H #ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MMU_H #define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000) #define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x) #define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x) #define __bus_to_virt(x) __phys_to_virt(x)
#endif #endif

7
include/asm-arm/arch-orion/orion.h
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@ -11,8 +11,8 @@
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
#ifndef __ASM_ARCH_ORION_H__ #ifndef __ASM_ARCH_ORION_H
#define __ASM_ARCH_ORION_H__ #define __ASM_ARCH_ORION_H
/***************************************************************************** /*****************************************************************************
* Orion Address Maps * Orion Address Maps
@ -91,6 +91,7 @@
#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
@ -154,7 +155,5 @@
#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) #define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) #define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
#endif #endif

5
include/asm-arm/arch-orion/system.h
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@ -3,8 +3,8 @@
* *
* Tzachi Perelstein <tzachi@marvell.com> * Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
@ -28,4 +28,5 @@ static inline void arch_reset(char mode)
orion_setbits(CPU_SOFT_RESET, 1); orion_setbits(CPU_SOFT_RESET, 1);
} }
#endif #endif

4
include/asm-arm/arch-orion/timex.h
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@ -3,8 +3,8 @@
* *
* Tzachi Perelstein <tzachi@marvell.com> * Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */

4
include/asm-arm/arch-orion/uncompress.h
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@ -3,8 +3,8 @@
* *
* Tzachi Perelstein <tzachi@marvell.com> * Tzachi Perelstein <tzachi@marvell.com>
* *
* This file is licensed under the terms of the GNU General Public * This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */