crypto: cavium - switch to pci_alloc_irq_vectors
pci_enable_msix has been long deprecated, but this driver adds a new instance. Convert it to pci_alloc_irq_vectors and greatly simplify the code, and make sure the prope code properly unwinds. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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613844e811
Коммит
15c0b9edcc
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@ -107,9 +107,6 @@ struct cpt_vf {
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void __iomem *reg_base; /* Register start address */
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void *wqe_info; /* BH worker info */
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/* MSI-X */
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bool msix_enabled;
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struct msix_entry msix_entries[CPT_VF_MSIX_VECTORS];
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bool irq_allocated[CPT_VF_MSIX_VECTORS];
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cpumask_var_t affinity_mask[CPT_VF_MSIX_VECTORS];
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/* Command and Pending queues */
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u32 qsize;
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@ -357,48 +357,10 @@ setup_pqfail:
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return ret;
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}
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static void cptvf_disable_msix(struct cpt_vf *cptvf)
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static void cptvf_free_irq_affinity(struct cpt_vf *cptvf, int vec)
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{
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if (cptvf->msix_enabled) {
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pci_disable_msix(cptvf->pdev);
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cptvf->msix_enabled = 0;
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}
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}
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static int cptvf_enable_msix(struct cpt_vf *cptvf)
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{
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int i, ret;
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for (i = 0; i < CPT_VF_MSIX_VECTORS; i++)
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cptvf->msix_entries[i].entry = i;
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ret = pci_enable_msix(cptvf->pdev, cptvf->msix_entries,
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CPT_VF_MSIX_VECTORS);
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if (ret) {
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dev_err(&cptvf->pdev->dev, "Request for #%d msix vectors failed\n",
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CPT_VF_MSIX_VECTORS);
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return ret;
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}
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cptvf->msix_enabled = 1;
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/* Mark MSIX enabled */
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cptvf->flags |= CPT_FLAG_MSIX_ENABLED;
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return 0;
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}
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static void cptvf_free_all_interrupts(struct cpt_vf *cptvf)
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{
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int irq;
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for (irq = 0; irq < CPT_VF_MSIX_VECTORS; irq++) {
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if (cptvf->irq_allocated[irq])
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irq_set_affinity_hint(cptvf->msix_entries[irq].vector,
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NULL);
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free_cpumask_var(cptvf->affinity_mask[irq]);
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free_irq(cptvf->msix_entries[irq].vector, cptvf);
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cptvf->irq_allocated[irq] = false;
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}
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irq_set_affinity_hint(pci_irq_vector(cptvf->pdev, vec), NULL);
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free_cpumask_var(cptvf->affinity_mask[vec]);
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}
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static void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val)
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@ -650,85 +612,23 @@ static irqreturn_t cptvf_done_intr_handler(int irq, void *cptvf_irq)
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return IRQ_HANDLED;
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}
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static int cptvf_register_misc_intr(struct cpt_vf *cptvf)
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static void cptvf_set_irq_affinity(struct cpt_vf *cptvf, int vec)
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{
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struct pci_dev *pdev = cptvf->pdev;
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int ret;
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int cpu;
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/* Register misc interrupt handlers */
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ret = request_irq(cptvf->msix_entries[CPT_VF_INT_VEC_E_MISC].vector,
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cptvf_misc_intr_handler, 0, "CPT VF misc intr",
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cptvf);
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if (ret)
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goto fail;
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cptvf->irq_allocated[CPT_VF_INT_VEC_E_MISC] = true;
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/* Enable mailbox interrupt */
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cptvf_enable_mbox_interrupts(cptvf);
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cptvf_enable_swerr_interrupts(cptvf);
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return 0;
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fail:
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dev_err(&pdev->dev, "Request misc irq failed");
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cptvf_free_all_interrupts(cptvf);
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return ret;
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}
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static int cptvf_register_done_intr(struct cpt_vf *cptvf)
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{
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struct pci_dev *pdev = cptvf->pdev;
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int ret;
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/* Register DONE interrupt handlers */
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ret = request_irq(cptvf->msix_entries[CPT_VF_INT_VEC_E_DONE].vector,
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cptvf_done_intr_handler, 0, "CPT VF done intr",
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cptvf);
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if (ret)
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goto fail;
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cptvf->irq_allocated[CPT_VF_INT_VEC_E_DONE] = true;
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/* Enable mailbox interrupt */
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cptvf_enable_done_interrupts(cptvf);
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return 0;
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fail:
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dev_err(&pdev->dev, "Request done irq failed\n");
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cptvf_free_all_interrupts(cptvf);
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return ret;
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}
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static void cptvf_unregister_interrupts(struct cpt_vf *cptvf)
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{
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cptvf_free_all_interrupts(cptvf);
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cptvf_disable_msix(cptvf);
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}
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static void cptvf_set_irq_affinity(struct cpt_vf *cptvf)
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{
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struct pci_dev *pdev = cptvf->pdev;
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int vec, cpu;
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int irqnum;
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for (vec = 0; vec < CPT_VF_MSIX_VECTORS; vec++) {
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if (!cptvf->irq_allocated[vec])
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continue;
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if (!zalloc_cpumask_var(&cptvf->affinity_mask[vec],
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GFP_KERNEL)) {
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dev_err(&pdev->dev, "Allocation failed for affinity_mask for VF %d",
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cptvf->vfid);
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return;
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}
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cpu = cptvf->vfid % num_online_cpus();
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cpumask_set_cpu(cpumask_local_spread(cpu, cptvf->node),
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cptvf->affinity_mask[vec]);
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irqnum = cptvf->msix_entries[vec].vector;
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irq_set_affinity_hint(irqnum, cptvf->affinity_mask[vec]);
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if (!zalloc_cpumask_var(&cptvf->affinity_mask[vec],
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GFP_KERNEL)) {
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dev_err(&pdev->dev, "Allocation failed for affinity_mask for VF %d",
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cptvf->vfid);
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return;
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}
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cpu = cptvf->vfid % num_online_cpus();
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cpumask_set_cpu(cpumask_local_spread(cpu, cptvf->node),
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cptvf->affinity_mask[vec]);
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irq_set_affinity_hint(pci_irq_vector(pdev, vec),
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cptvf->affinity_mask[vec]);
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}
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static void cptvf_write_vq_saddr(struct cpt_vf *cptvf, u64 val)
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@ -809,22 +709,32 @@ static int cptvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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cptvf->node = dev_to_node(&pdev->dev);
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/* Enable MSI-X */
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err = cptvf_enable_msix(cptvf);
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if (err) {
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dev_err(dev, "cptvf_enable_msix() failed");
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err = pci_alloc_irq_vectors(pdev, CPT_VF_MSIX_VECTORS,
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CPT_VF_MSIX_VECTORS, PCI_IRQ_MSIX);
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if (err < 0) {
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dev_err(dev, "Request for #%d msix vectors failed\n",
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CPT_VF_MSIX_VECTORS);
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goto cptvf_err_release_regions;
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}
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/* Register mailbox interrupts */
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cptvf_register_misc_intr(cptvf);
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err = request_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC),
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cptvf_misc_intr_handler, 0, "CPT VF misc intr",
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cptvf);
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if (err) {
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dev_err(dev, "Request misc irq failed");
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goto cptvf_free_vectors;
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}
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/* Enable mailbox interrupt */
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cptvf_enable_mbox_interrupts(cptvf);
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cptvf_enable_swerr_interrupts(cptvf);
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/* Check ready with PF */
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/* Gets chip ID / device Id from PF if ready */
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err = cptvf_check_pf_ready(cptvf);
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if (err) {
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dev_err(dev, "PF not responding to READY msg");
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goto cptvf_err_release_regions;
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goto cptvf_free_misc_irq;
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}
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/* CPT VF software resources initialization */
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@ -832,13 +742,13 @@ static int cptvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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err = cptvf_sw_init(cptvf, CPT_CMD_QLEN, CPT_NUM_QS_PER_VF);
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if (err) {
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dev_err(dev, "cptvf_sw_init() failed");
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goto cptvf_err_release_regions;
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goto cptvf_free_misc_irq;
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}
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/* Convey VQ LEN to PF */
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err = cptvf_send_vq_size_msg(cptvf);
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if (err) {
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dev_err(dev, "PF not responding to QLEN msg");
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goto cptvf_err_release_regions;
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goto cptvf_free_misc_irq;
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}
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/* CPT VF device initialization */
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@ -848,37 +758,50 @@ static int cptvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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err = cptvf_send_vf_to_grp_msg(cptvf);
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if (err) {
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dev_err(dev, "PF not responding to VF_GRP msg");
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goto cptvf_err_release_regions;
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goto cptvf_free_misc_irq;
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}
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cptvf->priority = 1;
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err = cptvf_send_vf_priority_msg(cptvf);
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if (err) {
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dev_err(dev, "PF not responding to VF_PRIO msg");
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goto cptvf_err_release_regions;
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goto cptvf_free_misc_irq;
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}
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/* Register DONE interrupts */
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err = cptvf_register_done_intr(cptvf);
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if (err)
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goto cptvf_err_release_regions;
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err = request_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_DONE),
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cptvf_done_intr_handler, 0, "CPT VF done intr",
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cptvf);
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if (err) {
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dev_err(dev, "Request done irq failed\n");
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goto cptvf_free_misc_irq;
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}
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/* Enable mailbox interrupt */
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cptvf_enable_done_interrupts(cptvf);
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/* Set irq affinity masks */
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cptvf_set_irq_affinity(cptvf);
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/* Convey UP to PF */
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cptvf_set_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC);
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cptvf_set_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE);
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err = cptvf_send_vf_up(cptvf);
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if (err) {
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dev_err(dev, "PF not responding to UP msg");
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goto cptvf_up_fail;
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goto cptvf_free_irq_affinity;
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}
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err = cvm_crypto_init(cptvf);
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if (err) {
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dev_err(dev, "Algorithm register failed\n");
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goto cptvf_up_fail;
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goto cptvf_free_irq_affinity;
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}
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return 0;
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cptvf_up_fail:
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cptvf_unregister_interrupts(cptvf);
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cptvf_free_irq_affinity:
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cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE);
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cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC);
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cptvf_free_misc_irq:
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free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC), cptvf);
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cptvf_free_vectors:
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pci_free_irq_vectors(cptvf->pdev);
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cptvf_err_release_regions:
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pci_release_regions(pdev);
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cptvf_err_disable_device:
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@ -899,7 +822,11 @@ static void cptvf_remove(struct pci_dev *pdev)
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if (cptvf_send_vf_down(cptvf)) {
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dev_err(&pdev->dev, "PF not responding to DOWN msg");
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} else {
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cptvf_unregister_interrupts(cptvf);
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cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE);
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cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC);
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free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_DONE), cptvf);
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free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC), cptvf);
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pci_free_irq_vectors(cptvf->pdev);
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cptvf_sw_cleanup(cptvf);
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pci_set_drvdata(pdev, NULL);
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pci_release_regions(pdev);
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