ARM: move CP15 definitions to separate header file
Avoid namespace conflicts with drivers over the CP15 definitions by moving CP15 related prototypes and definitions to a private header file. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra] Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx] Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
Russell King
David Howells
Родитель
ec2212088c
Коммит
15d07dc9c5
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@ -0,0 +1,87 @@
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#ifndef __ASM_ARM_CP15_H
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#define __ASM_ARM_CP15_H
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#include <asm/system.h>
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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#ifndef __ASSEMBLY__
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#if __LINUX_ARM_ARCH__ >= 4
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#define vectors_high() (cr_alignment & CR_V)
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#else
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#define vectors_high() (0)
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#endif
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifndef CONFIG_SMP
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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isb();
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}
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#endif
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#endif
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@ -14,37 +14,6 @@
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#define CPU_ARCH_ARMv6 8
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#define CPU_ARCH_ARMv7 9
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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@ -119,12 +88,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd);
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extern unsigned int user_debug;
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#if __LINUX_ARM_ARCH__ >= 4
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#define vectors_high() (cr_alignment & CR_V)
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#else
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#define vectors_high() (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 7 || \
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(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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@ -185,46 +148,6 @@ extern unsigned int user_debug;
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifndef CONFIG_SMP
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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isb();
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}
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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@ -42,9 +42,9 @@
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#include <linux/seq_file.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/fiq.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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static unsigned long no_fiq_insn;
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@ -17,8 +17,8 @@
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/cp15.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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/*
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* Kernel startup entry point.
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@ -15,12 +15,12 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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#include <asm/domain.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_DEBUG_LL
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@ -33,6 +33,7 @@
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#include <linux/sort.h>
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#include <asm/unified.h>
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#include <asm/cp15.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/elf.h>
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@ -44,7 +45,6 @@
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/tlbflush.h>
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#include <asm/system.h>
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#include <asm/prom.h>
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#include <asm/mach/arch.h>
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@ -16,6 +16,7 @@
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <mach/regs-pmu.h>
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@ -13,6 +13,7 @@
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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extern volatile int pen_release;
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@ -13,6 +13,7 @@
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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static inline void cpu_enter_lowpower(void)
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{
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@ -14,7 +14,7 @@
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/system.h>
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#include <asm/cp15.h>
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extern volatile int pen_release;
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@ -22,7 +22,7 @@
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#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <asm/system.h>
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#include <asm/cp15.h>
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#include <asm/unaligned.h>
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#include "fault.h"
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@ -15,6 +15,7 @@
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <plat/cache-feroceon-l2.h>
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/*
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@ -16,6 +16,7 @@
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#include <linux/init.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/hardware/cache-tauros2.h>
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@ -18,7 +18,7 @@
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*/
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <asm/system.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/cacheflush.h>
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@ -26,6 +26,7 @@
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#include <linux/vmalloc.h>
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#include <linux/io.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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@ -17,6 +17,7 @@
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#include <linux/fs.h>
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#include <linux/vmalloc.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/sections.h>
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#include <asm/cachetype.h>
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@ -12,6 +12,7 @@
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#include <linux/highmem.h>
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#include <linux/slab.h>
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#include <asm/cp15.h>
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#include <asm/pgalloc.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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@ -18,6 +18,7 @@
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/thread_notify.h>
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#include <asm/vfp.h>
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