drivers/net/phy: add the link modes for the 10BASE-T1S Ethernet PHY
This patch adds the link modes for the IEEE 802.3cg Clause 147 10BASE-T1S Ethernet PHY. According to the specifications, the 10BASE-T1S supports Point-To-Point Full-Duplex, Point-To-Point Half-Duplex and/or Point-To-Multipoint (AKA Multi-Drop) Half-Duplex operations. Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Piergiorgio Beruto
David S. Miller
Родитель
8580e16c28
Коммит
16178c8ef5
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@ -13,7 +13,7 @@
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*/
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const char *phy_speed_to_str(int speed)
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{
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BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,
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BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102,
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"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
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"If a speed or mode has been added please update phy_speed_to_str "
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"and the PHY settings array.\n");
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@ -260,6 +260,9 @@ static const struct phy_setting settings[] = {
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PHY_SETTING( 10, FULL, 10baseT_Full ),
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PHY_SETTING( 10, HALF, 10baseT_Half ),
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PHY_SETTING( 10, FULL, 10baseT1L_Full ),
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PHY_SETTING( 10, FULL, 10baseT1S_Full ),
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PHY_SETTING( 10, HALF, 10baseT1S_Half ),
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PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ),
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};
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#undef PHY_SETTING
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@ -45,6 +45,9 @@ EXPORT_SYMBOL_GPL(phy_basic_features);
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__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
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EXPORT_SYMBOL_GPL(phy_basic_t1_features);
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__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
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EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features);
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__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
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EXPORT_SYMBOL_GPL(phy_gbit_features);
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@ -98,6 +101,12 @@ const int phy_basic_t1_features_array[3] = {
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};
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EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
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const int phy_basic_t1s_p2mp_features_array[2] = {
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ETHTOOL_LINK_MODE_TP_BIT,
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ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT,
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};
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EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features_array);
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const int phy_gbit_features_array[2] = {
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ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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@ -138,6 +147,11 @@ static void features_init(void)
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ARRAY_SIZE(phy_basic_t1_features_array),
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phy_basic_t1_features);
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/* 10 half, P2MP, TP */
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linkmode_set_bit_array(phy_basic_t1s_p2mp_features_array,
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ARRAY_SIZE(phy_basic_t1s_p2mp_features_array),
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phy_basic_t1s_p2mp_features);
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/* 10/100 half/full + 1000 half/full */
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linkmode_set_bit_array(phy_basic_ports_array,
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ARRAY_SIZE(phy_basic_ports_array),
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@ -241,12 +241,16 @@ void phylink_caps_to_linkmodes(unsigned long *linkmodes, unsigned long caps)
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if (caps & MAC_ASYM_PAUSE)
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__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, linkmodes);
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if (caps & MAC_10HD)
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if (caps & MAC_10HD) {
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes);
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__set_bit(ETHTOOL_LINK_MODE_10baseT1S_Half_BIT, linkmodes);
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__set_bit(ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT, linkmodes);
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}
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if (caps & MAC_10FD) {
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__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes);
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__set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, linkmodes);
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__set_bit(ETHTOOL_LINK_MODE_10baseT1S_Full_BIT, linkmodes);
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}
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if (caps & MAC_100HD) {
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@ -45,6 +45,7 @@
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
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extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
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@ -54,6 +55,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_ini
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#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
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#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
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#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
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#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
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#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
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#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
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@ -66,6 +68,7 @@ extern const int phy_fibre_port_array[1];
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extern const int phy_all_ports_features_array[7];
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extern const int phy_10_100_features_array[4];
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extern const int phy_basic_t1_features_array[3];
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extern const int phy_basic_t1s_p2mp_features_array[2];
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extern const int phy_gbit_features_array[2];
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extern const int phy_10gbit_features_array[1];
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@ -1041,6 +1044,17 @@ struct phy_driver {
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int (*get_sqi)(struct phy_device *dev);
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/** @get_sqi_max: Get the maximum signal quality indication */
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int (*get_sqi_max)(struct phy_device *dev);
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/* PLCA RS interface */
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/** @get_plca_cfg: Return the current PLCA configuration */
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int (*get_plca_cfg)(struct phy_device *dev,
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struct phy_plca_cfg *plca_cfg);
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/** @set_plca_cfg: Set the PLCA configuration */
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int (*set_plca_cfg)(struct phy_device *dev,
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const struct phy_plca_cfg *plca_cfg);
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/** @get_plca_status: Return the current PLCA status info */
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int (*get_plca_status)(struct phy_device *dev,
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struct phy_plca_status *plca_st);
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};
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#define to_phy_driver(d) container_of(to_mdio_common_driver(d), \
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struct phy_driver, mdiodrv)
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@ -1741,6 +1741,9 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,
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ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,
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ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,
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ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99,
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ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,
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ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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@ -208,6 +208,9 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
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__DEFINE_LINK_MODE_NAME(800000, DR8_2, Full),
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__DEFINE_LINK_MODE_NAME(800000, SR8, Full),
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__DEFINE_LINK_MODE_NAME(800000, VR8, Full),
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__DEFINE_LINK_MODE_NAME(10, T1S, Full),
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__DEFINE_LINK_MODE_NAME(10, T1S, Half),
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__DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half),
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};
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static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
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@ -244,6 +247,8 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
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#define __LINK_MODE_LANES_X 1
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#define __LINK_MODE_LANES_FX 1
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#define __LINK_MODE_LANES_T1L 1
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#define __LINK_MODE_LANES_T1S 1
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#define __LINK_MODE_LANES_T1S_P2MP 1
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#define __LINK_MODE_LANES_VR8 8
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#define __LINK_MODE_LANES_DR8_2 8
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@ -366,6 +371,9 @@ const struct link_mode_info link_mode_params[] = {
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__DEFINE_LINK_MODE_PARAMS(800000, DR8_2, Full),
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__DEFINE_LINK_MODE_PARAMS(800000, SR8, Full),
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__DEFINE_LINK_MODE_PARAMS(800000, VR8, Full),
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__DEFINE_LINK_MODE_PARAMS(10, T1S, Full),
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__DEFINE_LINK_MODE_PARAMS(10, T1S, Half),
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__DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half),
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};
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static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
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