net: aquantia: added vlan offload related macros and functions
Register declaration macros required to work with vlan offload mode. Tested-by: Nikita Danilov <ndanilov@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -107,10 +107,17 @@
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#define HW_ATL_B0_RXD_NCEA0 (0x1)
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#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
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#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT (0x0)
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#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
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#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT (0x4)
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#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
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#define HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT (0x13)
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#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
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#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
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#define HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT (0x16)
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#define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN BIT(5)
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#define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE BIT(6)
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#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
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#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
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@ -1004,6 +1004,22 @@ void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
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rx_desc_vlan_stripping);
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}
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void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
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u32 outervlantagmode)
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{
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aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
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HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
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HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
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outervlantagmode);
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}
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u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
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{
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return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
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HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
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HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
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}
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void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
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u32 tcp_udp_crc_offload_en)
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{
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@ -488,6 +488,11 @@ void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
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u32 rx_desc_vlan_stripping,
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u32 descriptor);
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void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
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u32 outervlantagmode);
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u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context);
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/* set tcp/udp checksum offload enable */
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void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
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u32 tcp_udp_crc_offload_en);
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@ -1383,6 +1383,24 @@
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/* default value of bitfield l4_chk_en */
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#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0
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/* RX outer_vl_ins_mode Bitfield Definitions
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* Preprocessor definitions for the bitfield "outer_vl_ins_mode".
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* PORT="pif_rpo_outer_vl_mode_i"
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*/
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/* Register address for bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580
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/* Bitmask for bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004
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/* Inverted bitmask for bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB
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/* Lower bit position of bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2
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/* Width of bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1
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/* Default value of bitfield outer_vl_ins_mode */
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#define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0
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/* rx reg_res_dsbl bitfield definitions
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* preprocessor definitions for the bitfield "reg_res_dsbl".
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* port="pif_rx_reg_res_dsbl_i"
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