x86/events, drivers/amd/iommu: Prepare for multiple IOMMUs support
Currently, amd_iommu_pc_get_set_reg_val() cannot support multiple IOMMUs. Modify it to allow callers to specify an IOMMU. This is in preparation for supporting multiple IOMMUs. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Jörg Rödel <joro@8bytes.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/1487926102-13073-8-git-send-email-Suravee.Suthikulpanit@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -248,49 +248,45 @@ static int perf_iommu_event_init(struct perf_event *event)
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static void perf_iommu_enable_event(struct perf_event *ev)
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{
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struct amd_iommu *iommu = get_amd_iommu(0);
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u8 csource = _GET_CSOURCE(ev);
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u16 devid = _GET_DEVID(ev);
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u8 bank = _GET_BANK(ev);
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u8 cntr = _GET_CNTR(ev);
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u64 reg = 0ULL;
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reg = csource;
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_COUNTER_SRC_REG, ®, true);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®);
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reg = devid | (_GET_DEVID_MASK(ev) << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_DEVID_MATCH_REG, ®, true);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®);
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reg = _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_PASID_MATCH_REG, ®, true);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®);
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reg = _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32);
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if (reg)
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reg |= BIT(31);
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amd_iommu_pc_get_set_reg_val(devid,
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_GET_BANK(ev), _GET_CNTR(ev) ,
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IOMMU_PC_DOMID_MATCH_REG, ®, true);
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amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®);
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}
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static void perf_iommu_disable_event(struct perf_event *event)
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{
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struct amd_iommu *iommu = get_amd_iommu(0);
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u64 reg = 0ULL;
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_SRC_REG, ®, true);
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amd_iommu_pc_set_reg(iommu, _GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_SRC_REG, ®);
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}
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static void perf_iommu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amd_iommu *iommu = get_amd_iommu(0);
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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@ -300,9 +296,8 @@ static void perf_iommu_start(struct perf_event *event, int flags)
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if (flags & PERF_EF_RELOAD) {
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u64 prev_raw_count = local64_read(&hwc->prev_count);
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &prev_raw_count, true);
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amd_iommu_pc_set_reg(iommu, _GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &prev_raw_count);
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}
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perf_iommu_enable_event(event);
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@ -314,10 +309,11 @@ static void perf_iommu_read(struct perf_event *event)
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{
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u64 count, prev, delta;
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struct hw_perf_event *hwc = &event->hw;
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struct amd_iommu *iommu = get_amd_iommu(0);
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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_GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &count, false);
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if (amd_iommu_pc_get_reg(iommu, _GET_BANK(event), _GET_CNTR(event),
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IOMMU_PC_COUNTER_REG, &count))
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return;
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/* IOMMU pc counter register is only 48 bits */
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count &= GENMASK_ULL(47, 0);
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@ -24,6 +24,8 @@
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#define PC_MAX_SPEC_BNKS 64
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#define PC_MAX_SPEC_CNTRS 16
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struct amd_iommu;
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/* amd_iommu_init.c external support functions */
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extern int amd_iommu_get_num_iommus(void);
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@ -33,8 +35,11 @@ extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr,
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u8 fxn, u64 *value, bool is_write);
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extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern struct amd_iommu *get_amd_iommu(int idx);
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@ -256,10 +256,6 @@ static int amd_iommu_enable_interrupts(void);
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static int __init iommu_go_to_state(enum iommu_init_state state);
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static void init_device_table_dma(void);
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static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
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u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write);
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static inline void update_last_devid(u16 devid)
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{
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if (devid > amd_iommu_last_bdf)
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@ -1484,6 +1480,8 @@ static int __init init_iommu_all(struct acpi_table_header *table)
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return 0;
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}
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static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value, bool is_write);
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static void init_iommu_perf_ctr(struct amd_iommu *iommu)
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{
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@ -1495,8 +1493,8 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu)
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amd_iommu_pc_present = true;
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/* Check if the performance counters can be written to */
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if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
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(0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
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if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
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(iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
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(val != val2)) {
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pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
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amd_iommu_pc_present = false;
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@ -2765,15 +2763,18 @@ u8 amd_iommu_pc_get_max_counters(unsigned int idx)
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}
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EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
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static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
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u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write)
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static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value, bool is_write)
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{
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u32 offset;
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u32 max_offset_lim;
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/* Make sure the IOMMU PC resource is available */
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if (!amd_iommu_pc_present)
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return -ENODEV;
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/* Check for valid iommu and pc register indexing */
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if (WARN_ON((fxn > 0x28) || (fxn & 7)))
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if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
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return -ENODEV;
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offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
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@ -2799,17 +2800,21 @@ static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
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return 0;
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}
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EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
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int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write)
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int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
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{
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struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
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if (!iommu)
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return -EINVAL;
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/* Make sure the IOMMU PC resource is available */
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if (!amd_iommu_pc_present || iommu == NULL)
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return -ENODEV;
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return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
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value, is_write);
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return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
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}
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EXPORT_SYMBOL(amd_iommu_pc_get_reg);
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int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
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{
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if (!iommu)
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return -EINVAL;
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return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
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}
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EXPORT_SYMBOL(amd_iommu_pc_set_reg);
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@ -57,11 +57,6 @@ extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
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extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid);
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extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
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/* IOMMU Performance Counter functions */
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extern bool amd_iommu_pc_supported(void);
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extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write);
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#ifdef CONFIG_IRQ_REMAP
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extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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