drm/radeon/kms: allocate vram scratch page on 6xx+
The vram scratch was originally only used on some 7xx asics to work around a hw bug. Allocate the scratch page on all 6xx+ radeons and set the MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR to point to it. We shouldn't ever hit it since we limit the system aperture to vram or vram and AGP, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
Родитель
996d5c5900
Коммит
16cdf04d30
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@ -3031,6 +3031,10 @@ static int evergreen_startup(struct radeon_device *rdev)
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}
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}
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r = r600_vram_scratch_init(rdev);
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if (r)
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return r;
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evergreen_mc_program(rdev);
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if (rdev->flags & RADEON_IS_AGP) {
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evergreen_agp_enable(rdev);
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@ -3235,6 +3239,7 @@ void evergreen_fini(struct radeon_device *rdev)
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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evergreen_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_agp_fini(rdev);
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@ -1361,6 +1361,10 @@ static int cayman_startup(struct radeon_device *rdev)
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return r;
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}
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r = r600_vram_scratch_init(rdev);
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if (r)
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return r;
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evergreen_mc_program(rdev);
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r = cayman_pcie_gart_enable(rdev);
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if (r)
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@ -1556,6 +1560,7 @@ void cayman_fini(struct radeon_device *rdev)
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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cayman_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_bo_fini(rdev);
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@ -1137,7 +1137,7 @@ static void r600_mc_program(struct radeon_device *rdev)
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WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
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}
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
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tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
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tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(MC_VM_FB_LOCATION, tmp);
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@ -1276,6 +1276,53 @@ int r600_mc_init(struct radeon_device *rdev)
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return 0;
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}
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int r600_vram_scratch_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->vram_scratch.robj == NULL) {
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r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
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PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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&rdev->vram_scratch.robj);
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if (r) {
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(rdev->vram_scratch.robj,
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RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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return r;
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}
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r = radeon_bo_kmap(rdev->vram_scratch.robj,
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(void **)&rdev->vram_scratch.ptr);
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if (r)
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radeon_bo_unpin(rdev->vram_scratch.robj);
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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return r;
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}
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void r600_vram_scratch_fini(struct radeon_device *rdev)
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{
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int r;
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if (rdev->vram_scratch.robj == NULL) {
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return;
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}
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r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(rdev->vram_scratch.robj);
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radeon_bo_unpin(rdev->vram_scratch.robj);
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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}
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radeon_bo_unref(&rdev->vram_scratch.robj);
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}
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/* We doesn't check that the GPU really needs a reset we simply do the
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* reset, it's up to the caller to determine if the GPU needs one. We
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* might add an helper function to check that.
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@ -2436,6 +2483,10 @@ int r600_startup(struct radeon_device *rdev)
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}
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}
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r = r600_vram_scratch_init(rdev);
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if (r)
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return r;
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r600_mc_program(rdev);
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if (rdev->flags & RADEON_IS_AGP) {
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r600_agp_enable(rdev);
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@ -2656,6 +2707,7 @@ void r600_fini(struct radeon_device *rdev)
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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r600_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_agp_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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@ -1144,10 +1144,11 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
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int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp);
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/* VRAM scratch page for HDP bug */
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struct r700_vram_scratch {
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/* VRAM scratch page for HDP bug, default vram page */
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struct r600_vram_scratch {
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struct radeon_bo *robj;
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volatile uint32_t *ptr;
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u64 gpu_addr;
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};
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/*
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@ -1219,7 +1220,7 @@ struct radeon_device {
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const struct firmware *rlc_fw; /* r6/700 RLC firmware */
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const struct firmware *mc_fw; /* NI MC firmware */
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struct r600_blit r600_blit;
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struct r700_vram_scratch vram_scratch;
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struct r600_vram_scratch vram_scratch;
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int msi_enabled; /* msi enabled */
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struct r600_ih ih; /* r6/700 interrupt ring */
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struct work_struct hotplug_work;
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@ -1467,6 +1468,12 @@ extern int radeon_resume_kms(struct drm_device *dev);
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extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
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extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
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/*
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* R600 vram scratch functions
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*/
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int r600_vram_scratch_init(struct radeon_device *rdev);
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void r600_vram_scratch_fini(struct radeon_device *rdev);
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/*
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* r600 functions used by radeon_encoder.c
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*/
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@ -282,7 +282,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
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WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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rdev->mc.vram_end >> 12);
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}
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
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WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
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tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
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tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(MC_VM_FB_LOCATION, tmp);
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@ -959,54 +959,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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}
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static int rv770_vram_scratch_init(struct radeon_device *rdev)
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{
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int r;
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u64 gpu_addr;
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if (rdev->vram_scratch.robj == NULL) {
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r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
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PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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&rdev->vram_scratch.robj);
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if (r) {
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(rdev->vram_scratch.robj,
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RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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return r;
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}
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r = radeon_bo_kmap(rdev->vram_scratch.robj,
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(void **)&rdev->vram_scratch.ptr);
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if (r)
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radeon_bo_unpin(rdev->vram_scratch.robj);
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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return r;
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}
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static void rv770_vram_scratch_fini(struct radeon_device *rdev)
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{
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int r;
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if (rdev->vram_scratch.robj == NULL) {
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return;
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}
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r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(rdev->vram_scratch.robj);
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radeon_bo_unpin(rdev->vram_scratch.robj);
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radeon_bo_unreserve(rdev->vram_scratch.robj);
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}
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radeon_bo_unref(&rdev->vram_scratch.robj);
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}
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void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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{
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u64 size_bf, size_af;
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@ -1106,6 +1058,10 @@ static int rv770_startup(struct radeon_device *rdev)
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}
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}
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r = r600_vram_scratch_init(rdev);
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if (r)
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return r;
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rv770_mc_program(rdev);
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if (rdev->flags & RADEON_IS_AGP) {
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rv770_agp_enable(rdev);
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@ -1114,9 +1070,7 @@ static int rv770_startup(struct radeon_device *rdev)
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if (r)
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return r;
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}
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r = rv770_vram_scratch_init(rdev);
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if (r)
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return r;
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rv770_gpu_init(rdev);
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r = r600_blit_init(rdev);
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if (r) {
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@ -1316,7 +1270,7 @@ void rv770_fini(struct radeon_device *rdev)
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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rv770_pcie_gart_fini(rdev);
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rv770_vram_scratch_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_agp_fini(rdev);
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