Merge branch 'net-phy-at803x-device-tree-binding'
Michael Walle says: ==================== net: phy: at803x device tree binding Adds a device tree binding to configure the clock and the RGMII voltage. Changes since v1: - rebased to latest net-next - renamed "Atheros" to "Qualcomm Atheros" - add a new patch to remove config_init() from AR9331 Changes since the RFC: - renamed the Kconfig entry to "Qualcomm Atheros.." and reordered the item - renamed the prefix from atheros to qca - use the correct name AR803x (instead of AT803x) in new files and dt-bindings. - listed the PHY maintainers in the new schema. Hopefully, thats ok. - fixed a typo in the bindings schema - run dtb_checks and dt_binding_check and fixed the schema - dropped the rgmii-io-1v8 property; instead provide two regulators vddh and vddio, add one consumer vddio-supply - fix the clock settings for the AR8030/AR8035 - only the AR8031 supports chaning the LDO and the PLL mode in software. Check if we have the correct PHY. - new patch to mention the AR8033 which is the same as the AR8031 just without PTP support - new patch which corrects any displayed PHY names and comments. Be consistent. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
16cf4222be
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@ -0,0 +1,111 @@
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# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Atheros AR803x PHY
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Florian Fainelli <f.fainelli@gmail.com>
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- Heiner Kallweit <hkallweit1@gmail.com>
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description: |
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Bindings for Qualcomm Atheros AR803x PHYs
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allOf:
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- $ref: ethernet-phy.yaml#
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properties:
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qca,clk-out-frequency:
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description: Clock output frequency in Hertz.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 25000000, 50000000, 62500000, 125000000 ]
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qca,clk-out-strength:
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description: Clock output driver strength.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 0, 1, 2 ]
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qca,keep-pll-enabled:
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description: |
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If set, keep the PLL enabled even if there is no link. Useful if you
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want to use the clock output without an ethernet link.
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Only supported on the AR8031.
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type: boolean
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vddio-supply:
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description: |
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RGMII I/O voltage regulator (see regulator/regulator.yaml).
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The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
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either connect this to the vddio-regulator (1.5V / 1.8V) or the
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vddh-regulator (2.5V).
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Only supported on the AR8031.
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vddio-regulator:
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type: object
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description:
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Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
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allOf:
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- $ref: /schemas/regulator/regulator.yaml
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vddh-regulator:
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type: object
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description:
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Dummy subnode to model the external connection of the PHY VDDH
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regulator to VDDIO.
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allOf:
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- $ref: /schemas/regulator/regulator.yaml
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examples:
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- |
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#include <dt-bindings/net/qca-ar803x.h>
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii-id";
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ethernet-phy@0 {
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reg = <0>;
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qca,clk-out-frequency = <125000000>;
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qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
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vddio-supply = <&vddio>;
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vddio: vddio-regulator {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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- |
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#include <dt-bindings/net/qca-ar803x.h>
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii-id";
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ethernet-phy@0 {
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reg = <0>;
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qca,clk-out-frequency = <50000000>;
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qca,keep-pll-enabled;
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vddio-supply = <&vddh>;
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vddh: vddh-regulator {
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};
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};
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};
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@ -6155,10 +6155,12 @@ S: Maintained
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F: Documentation/ABI/testing/sysfs-class-net-phydev
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F: Documentation/devicetree/bindings/net/ethernet-phy.yaml
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F: Documentation/devicetree/bindings/net/mdio*
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F: Documentation/devicetree/bindings/net/qca,ar803x.yaml
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F: Documentation/networking/phy.rst
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F: drivers/net/phy/
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F: drivers/of/of_mdio.c
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F: drivers/of/of_net.c
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F: include/dt-bindings/net/qca-ar803x.h
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F: include/linux/*mdio*.h
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F: include/linux/of_net.h
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F: include/linux/phy.h
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@ -282,11 +282,6 @@ config AX88796B_PHY
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Currently supports the Asix Electronics PHY found in the X-Surf 100
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AX88796B package.
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config AT803X_PHY
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tristate "AT803X PHYs"
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---help---
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Currently supports the AT8030 and AT8035 model
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config BCM63XX_PHY
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tristate "Broadcom 63xx SOCs internal PHY"
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depends on BCM63XX || COMPILE_TEST
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@ -444,6 +439,11 @@ config NXP_TJA11XX_PHY
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---help---
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Currently supports the NXP TJA1100 and TJA1101 PHY.
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config AT803X_PHY
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tristate "Qualcomm Atheros AR803X PHYs"
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help
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Currently supports the AR8030, AR8031, AR8033 and AR8035 model
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config QSEMI_PHY
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tristate "Quality Semiconductor PHYs"
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---help---
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@ -2,7 +2,7 @@
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/*
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* drivers/net/phy/at803x.c
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*
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* Driver for Atheros 803x PHY
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* Driver for Qualcomm Atheros AR803x PHY
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*
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* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
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*/
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@ -13,7 +13,12 @@
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/of_gpio.h>
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#include <linux/bitfield.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/net/qca-ar803x.h>
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#define AT803X_SPECIFIC_STATUS 0x11
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#define AT803X_SS_SPEED_MASK (3 << 14)
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@ -62,16 +67,62 @@
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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#define AT803X_DEBUG_REG_1F 0x1F
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#define AT803X_DEBUG_PLL_ON BIT(2)
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#define AT803X_DEBUG_RGMII_1V8 BIT(3)
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/* AT803x supports either the XTAL input pad, an internal PLL or the
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* DSP as clock reference for the clock output pad. The XTAL reference
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* is only used for 25 MHz output, all other frequencies need the PLL.
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* The DSP as a clock reference is used in synchronous ethernet
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* applications.
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*
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* By default the PLL is only enabled if there is a link. Otherwise
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* the PHY will go into low power state and disabled the PLL. You can
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* set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
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* enabled.
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*/
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#define AT803X_MMD7_CLK25M 0x8016
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#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
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#define AT803X_CLK_OUT_25MHZ_XTAL 0
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#define AT803X_CLK_OUT_25MHZ_DSP 1
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#define AT803X_CLK_OUT_50MHZ_PLL 2
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#define AT803X_CLK_OUT_50MHZ_DSP 3
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#define AT803X_CLK_OUT_62_5MHZ_PLL 4
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#define AT803X_CLK_OUT_62_5MHZ_DSP 5
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#define AT803X_CLK_OUT_125MHZ_PLL 6
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#define AT803X_CLK_OUT_125MHZ_DSP 7
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/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
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* but doesn't support choosing between XTAL/PLL and DSP.
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*/
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#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
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#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
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#define AT803X_CLK_OUT_STRENGTH_FULL 0
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#define AT803X_CLK_OUT_STRENGTH_HALF 1
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#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
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#define ATH9331_PHY_ID 0x004dd041
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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#define ATH8035_PHY_ID 0x004dd072
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#define AT803X_PHY_ID_MASK 0xffffffef
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MODULE_DESCRIPTION("Atheros 803x PHY driver");
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MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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struct at803x_priv {
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int flags;
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#define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
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u16 clk_25m_reg;
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u16 clk_25m_mask;
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struct regulator_dev *vddio_rdev;
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struct regulator_dev *vddh_rdev;
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struct regulator *vddio;
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};
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struct at803x_context {
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u16 bmcr;
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u16 advertise;
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@ -237,6 +288,240 @@ static int at803x_resume(struct phy_device *phydev)
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return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
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}
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static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
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unsigned int selector)
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{
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struct phy_device *phydev = rdev_get_drvdata(rdev);
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if (selector)
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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0, AT803X_DEBUG_RGMII_1V8);
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else
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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AT803X_DEBUG_RGMII_1V8, 0);
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}
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static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
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{
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struct phy_device *phydev = rdev_get_drvdata(rdev);
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int val;
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val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
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if (val < 0)
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return val;
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return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
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}
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static struct regulator_ops vddio_regulator_ops = {
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.list_voltage = regulator_list_voltage_table,
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.set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
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.get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
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};
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static const unsigned int vddio_voltage_table[] = {
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1500000,
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1800000,
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};
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static const struct regulator_desc vddio_desc = {
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.name = "vddio",
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.of_match = of_match_ptr("vddio-regulator"),
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.n_voltages = ARRAY_SIZE(vddio_voltage_table),
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.volt_table = vddio_voltage_table,
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.ops = &vddio_regulator_ops,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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};
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static struct regulator_ops vddh_regulator_ops = {
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};
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static const struct regulator_desc vddh_desc = {
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.name = "vddh",
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.of_match = of_match_ptr("vddh-regulator"),
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.n_voltages = 1,
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.fixed_uV = 2500000,
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.ops = &vddh_regulator_ops,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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};
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static int at8031_register_regulators(struct phy_device *phydev)
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{
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struct at803x_priv *priv = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct regulator_config config = { };
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config.dev = dev;
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config.driver_data = phydev;
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priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
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if (IS_ERR(priv->vddio_rdev)) {
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phydev_err(phydev, "failed to register VDDIO regulator\n");
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return PTR_ERR(priv->vddio_rdev);
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}
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priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
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if (IS_ERR(priv->vddh_rdev)) {
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phydev_err(phydev, "failed to register VDDH regulator\n");
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return PTR_ERR(priv->vddh_rdev);
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}
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return 0;
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}
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static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
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{
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return (phydev->phy_id & phydev->drv->phy_id_mask)
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== (phy_id & phydev->drv->phy_id_mask);
|
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}
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static int at803x_parse_dt(struct phy_device *phydev)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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struct at803x_priv *priv = phydev->priv;
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unsigned int sel, mask;
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u32 freq, strength;
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int ret;
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if (!IS_ENABLED(CONFIG_OF_MDIO))
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return 0;
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ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
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if (!ret) {
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mask = AT803X_CLK_OUT_MASK;
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switch (freq) {
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case 25000000:
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sel = AT803X_CLK_OUT_25MHZ_XTAL;
|
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break;
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case 50000000:
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sel = AT803X_CLK_OUT_50MHZ_PLL;
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break;
|
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case 62500000:
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sel = AT803X_CLK_OUT_62_5MHZ_PLL;
|
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break;
|
||||
case 125000000:
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sel = AT803X_CLK_OUT_125MHZ_PLL;
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break;
|
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default:
|
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phydev_err(phydev, "invalid qca,clk-out-frequency\n");
|
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return -EINVAL;
|
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}
|
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||||
priv->clk_25m_reg |= FIELD_PREP(mask, sel);
|
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priv->clk_25m_mask |= mask;
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||||
/* Fixup for the AR8030/AR8035. This chip has another mask and
|
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* doesn't support the DSP reference. Eg. the lowest bit of the
|
||||
* mask. The upper two bits select the same frequencies. Mask
|
||||
* the lowest bit here.
|
||||
*
|
||||
* Warning:
|
||||
* There was no datasheet for the AR8030 available so this is
|
||||
* just a guess. But the AR8035 is listed as pin compatible
|
||||
* to the AR8030 so there might be a good chance it works on
|
||||
* the AR8030 too.
|
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*/
|
||||
if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
|
||||
at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
|
||||
priv->clk_25m_reg &= ~AT8035_CLK_OUT_MASK;
|
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priv->clk_25m_mask &= ~AT8035_CLK_OUT_MASK;
|
||||
}
|
||||
}
|
||||
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||||
ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
|
||||
if (!ret) {
|
||||
priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
|
||||
switch (strength) {
|
||||
case AR803X_STRENGTH_FULL:
|
||||
priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
|
||||
break;
|
||||
case AR803X_STRENGTH_HALF:
|
||||
priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
|
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break;
|
||||
case AR803X_STRENGTH_QUARTER:
|
||||
priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
|
||||
break;
|
||||
default:
|
||||
phydev_err(phydev, "invalid qca,clk-out-strength\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
|
||||
* options.
|
||||
*/
|
||||
if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
|
||||
if (of_property_read_bool(node, "qca,keep-pll-enabled"))
|
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priv->flags |= AT803X_KEEP_PLL_ENABLED;
|
||||
|
||||
ret = at8031_register_regulators(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
|
||||
"vddio");
|
||||
if (IS_ERR(priv->vddio)) {
|
||||
phydev_err(phydev, "failed to get VDDIO regulator\n");
|
||||
return PTR_ERR(priv->vddio);
|
||||
}
|
||||
|
||||
ret = regulator_enable(priv->vddio);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at803x_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct device *dev = &phydev->mdio.dev;
|
||||
struct at803x_priv *priv;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
phydev->priv = priv;
|
||||
|
||||
return at803x_parse_dt(phydev);
|
||||
}
|
||||
|
||||
static int at803x_clk_out_config(struct phy_device *phydev)
|
||||
{
|
||||
struct at803x_priv *priv = phydev->priv;
|
||||
int val;
|
||||
|
||||
if (!priv->clk_25m_mask)
|
||||
return 0;
|
||||
|
||||
val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
val &= ~priv->clk_25m_mask;
|
||||
val |= priv->clk_25m_reg;
|
||||
|
||||
return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val);
|
||||
}
|
||||
|
||||
static int at8031_pll_config(struct phy_device *phydev)
|
||||
{
|
||||
struct at803x_priv *priv = phydev->priv;
|
||||
|
||||
/* The default after hardware reset is PLL OFF. After a soft reset, the
|
||||
* values are retained.
|
||||
*/
|
||||
if (priv->flags & AT803X_KEEP_PLL_ENABLED)
|
||||
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
|
||||
0, AT803X_DEBUG_PLL_ON);
|
||||
else
|
||||
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
|
||||
AT803X_DEBUG_PLL_ON, 0);
|
||||
}
|
||||
|
||||
static int at803x_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -259,8 +544,20 @@ static int at803x_config_init(struct phy_device *phydev)
|
|||
ret = at803x_enable_tx_delay(phydev);
|
||||
else
|
||||
ret = at803x_disable_tx_delay(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return ret;
|
||||
ret = at803x_clk_out_config(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
|
||||
ret = at8031_pll_config(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at803x_ack_interrupt(struct phy_device *phydev)
|
||||
|
|
@ -409,10 +706,11 @@ static int at803x_read_status(struct phy_device *phydev)
|
|||
|
||||
static struct phy_driver at803x_driver[] = {
|
||||
{
|
||||
/* ATHEROS 8035 */
|
||||
/* Qualcomm Atheros AR8035 */
|
||||
.phy_id = ATH8035_PHY_ID,
|
||||
.name = "Atheros 8035 ethernet",
|
||||
.name = "Qualcomm Atheros AR8035",
|
||||
.phy_id_mask = AT803X_PHY_ID_MASK,
|
||||
.probe = at803x_probe,
|
||||
.config_init = at803x_config_init,
|
||||
.set_wol = at803x_set_wol,
|
||||
.get_wol = at803x_get_wol,
|
||||
|
|
@ -423,10 +721,11 @@ static struct phy_driver at803x_driver[] = {
|
|||
.ack_interrupt = at803x_ack_interrupt,
|
||||
.config_intr = at803x_config_intr,
|
||||
}, {
|
||||
/* ATHEROS 8030 */
|
||||
/* Qualcomm Atheros AR8030 */
|
||||
.phy_id = ATH8030_PHY_ID,
|
||||
.name = "Atheros 8030 ethernet",
|
||||
.name = "Qualcomm Atheros AR8030",
|
||||
.phy_id_mask = AT803X_PHY_ID_MASK,
|
||||
.probe = at803x_probe,
|
||||
.config_init = at803x_config_init,
|
||||
.link_change_notify = at803x_link_change_notify,
|
||||
.set_wol = at803x_set_wol,
|
||||
|
|
@ -437,10 +736,11 @@ static struct phy_driver at803x_driver[] = {
|
|||
.ack_interrupt = at803x_ack_interrupt,
|
||||
.config_intr = at803x_config_intr,
|
||||
}, {
|
||||
/* ATHEROS 8031 */
|
||||
/* Qualcomm Atheros AR8031/AR8033 */
|
||||
.phy_id = ATH8031_PHY_ID,
|
||||
.name = "Atheros 8031 ethernet",
|
||||
.name = "Qualcomm Atheros AR8031/AR8033",
|
||||
.phy_id_mask = AT803X_PHY_ID_MASK,
|
||||
.probe = at803x_probe,
|
||||
.config_init = at803x_config_init,
|
||||
.set_wol = at803x_set_wol,
|
||||
.get_wol = at803x_get_wol,
|
||||
|
|
@ -454,8 +754,7 @@ static struct phy_driver at803x_driver[] = {
|
|||
}, {
|
||||
/* ATHEROS AR9331 */
|
||||
PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
|
||||
.name = "Atheros AR9331 built-in PHY",
|
||||
.config_init = at803x_config_init,
|
||||
.name = "Qualcomm Atheros AR9331 built-in PHY",
|
||||
.suspend = at803x_suspend,
|
||||
.resume = at803x_resume,
|
||||
/* PHY_BASIC_FEATURES */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Device Tree constants for the Qualcomm Atheros AR803x PHYs
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_QCA_AR803X_H
|
||||
#define _DT_BINDINGS_QCA_AR803X_H
|
||||
|
||||
#define AR803X_STRENGTH_FULL 0
|
||||
#define AR803X_STRENGTH_HALF 1
|
||||
#define AR803X_STRENGTH_QUARTER 2
|
||||
|
||||
#endif
|
||||
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