dt-bindings: mmc: convert arasan sdhci bindings to yaml
Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml will inherit properties from mmc-controller.yaml. 'sdhci' is no longer a valid name for node and should be changed to 'mmc'. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200701023346.3873-1-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Wan Ahmad Zainie
Ulf Hansson
Родитель
c624b49a40
Коммит
16ecd8f33c
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@ -1,192 +0,0 @@
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Device Tree Bindings for the Arasan SDHCI Controller
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The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
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Only deviations are documented here.
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[1] Documentation/devicetree/bindings/mmc/mmc.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
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Required Properties:
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- compatible: Compatibility string. One of:
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- "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
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- "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
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- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
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- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
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For this device it is strongly suggested to include clock-output-names and
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#clock-cells.
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- "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
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For this device it is strongly suggested to include clock-output-names and
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#clock-cells.
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- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
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Note: This binding has been deprecated and moved to [5].
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- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
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- reg: From mmc bindings: Register location and length.
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- clocks: From clock bindings: Handles to clock inputs.
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- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
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- interrupts: Interrupt specifier
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Required Properties for "arasan,sdhci-5.1":
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- phys: From PHY bindings: Phandle for the Generic PHY for arasan.
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- phy-names: MUST be "phy_arasan".
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Optional Properties:
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- arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
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used to access core corecfg registers. Offsets of registers in this
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syscon are determined based on the main compatible string for the device.
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- clock-output-names: If specified, this will be the name of the card clock
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which will be exposed by this device. Required if #clock-cells is
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specified.
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- #clock-cells: If specified this should be the value <0> or <1>. With this
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property in place we will export one or two clocks representing the Card
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Clock. These clocks are expected to be consumed by our PHY.
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- xlnx,fails-without-test-cd: when present, the controller doesn't work when
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the CD line is not connected properly, and the line is not connected
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properly. Test mode can be used to force the controller to function.
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- xlnx,int-clock-stable-broken: when present, the controller always reports
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that the internal clock is stable even when it is not.
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- xlnx,mio-bank: When specified, this will indicate the MIO bank number in
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which the command and data lines are configured. If not specified, driver
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will assume this as 0.
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Example:
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sdhci@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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reg = <0xe0100000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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} ;
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sdhci@e2800000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0xe2800000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&cru 8>, <&cru 18>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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} ;
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sdhci: sdhci@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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arasan,soc-ctl-syscon = <&grf>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "emmc_cardclock";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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#clock-cells = <0>;
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};
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sdhci: mmc@ff160000 {
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compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
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interrupt-parent = <&gic>;
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interrupts = <0 48 4>;
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reg = <0x0 0xff160000 0x0 0x1000>;
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clocks = <&clk200>, <&clk200>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "clk_out_sd0", "clk_in_sd0";
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#clock-cells = <1>;
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clk-phase-sd-hs = <63>, <72>;
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};
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sdhci: mmc@f1040000 {
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compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
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interrupt-parent = <&gic>;
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interrupts = <0 126 4>;
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reg = <0x0 0xf1040000 0x0 0x10000>;
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clocks = <&clk200>, <&clk200>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "clk_out_sd0", "clk_in_sd0";
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#clock-cells = <1>;
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clk-phase-sd-hs = <132>, <60>;
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};
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emmc: sdhci@ec700000 {
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compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
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reg = <0xec700000 0x300>;
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interrupt-parent = <&ioapic1>;
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interrupts = <44 1>;
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clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
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<&cgu0 LGM_GCLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb", "gate";
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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arasan,soc-ctl-syscon = <&sysconf>;
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};
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sdxc: sdhci@ec600000 {
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compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
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reg = <0xec600000 0x300>;
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interrupt-parent = <&ioapic1>;
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interrupts = <43 1>;
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clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
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<&cgu0 LGM_GCLK_SDXC>;
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clock-names = "clk_xin", "clk_ahb", "gate";
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clock-output-names = "sdxc_cardclock";
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#clock-cells = <0>;
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phys = <&sdxc_phy>;
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phy-names = "phy_arasan";
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arasan,soc-ctl-syscon = <&sysconf>;
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};
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mmc: mmc@33000000 {
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compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x33000000 0x0 0x300>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
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<&scmi_clk KEEM_BAY_PSS_EMMC>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
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};
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sd0: mmc@31000000 {
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compatible = "intel,keembay-sdhci-5.1-sd";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x31000000 0x0 0x300>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
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<&scmi_clk KEEM_BAY_PSS_SD0>;
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arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
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};
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sd1: mmc@32000000 {
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compatible = "intel,keembay-sdhci-5.1-sdio";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x32000000 0x0 0x300>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
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<&scmi_clk KEEM_BAY_PSS_SD1>;
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arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
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};
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@ -0,0 +1,299 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Device Tree Bindings for the Arasan SDHCI Controller
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maintainers:
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- Adrian Hunter <adrian.hunter@intel.com>
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allOf:
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- $ref: "mmc-controller.yaml#"
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- if:
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properties:
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compatible:
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contains:
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const: arasan,sdhci-5.1
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then:
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required:
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- phys
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- phy-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- xlnx,zynqmp-8.9a
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- xlnx,versal-8.9a
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then:
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properties:
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clock-output-names:
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items:
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- const: clk_out_sd0
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- const: clk_in_sd0
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properties:
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compatible:
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oneOf:
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- const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
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- const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
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- const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
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- items:
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- const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
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- const: arasan,sdhci-8.9a
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description:
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For this device it is strongly suggested to include
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clock-output-names and '#clock-cells'.
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- items:
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- const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
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- const: arasan,sdhci-8.9a
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description:
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For this device it is strongly suggested to include
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clock-output-names and '#clock-cells'.
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- items:
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- const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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reg:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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items:
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- const: clk_xin
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- const: clk_ahb
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- const: gate
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interrupts:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: phy_arasan
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arasan,soc-ctl-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A phandle to a syscon device (see ../mfd/syscon.txt) used to access
|
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core corecfg registers. Offsets of registers in this syscon are
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determined based on the main compatible string for the device.
|
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|
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clock-output-names:
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minItems: 1
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maxItems: 2
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description:
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Name of the card clock which will be exposed by this device.
|
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|
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'#clock-cells':
|
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enum: [0, 1]
|
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description:
|
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With this property in place we will export one or two clocks
|
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representing the Card Clock. These clocks are expected to be
|
||||
consumed by our PHY.
|
||||
|
||||
xlnx,fails-without-test-cd:
|
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$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When present, the controller doesn't work when the CD line is not
|
||||
connected properly, and the line is not connected properly.
|
||||
Test mode can be used to force the controller to function.
|
||||
|
||||
xlnx,int-clock-stable-broken:
|
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$ref: /schemas/types.yaml#/definitions/flag
|
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description:
|
||||
When present, the controller always reports that the internal clock
|
||||
is stable even when it is not.
|
||||
|
||||
xlnx,mio-bank:
|
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$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 2]
|
||||
default: 0
|
||||
description:
|
||||
The MIO bank number in which the command and data lines are configured.
|
||||
|
||||
dependencies:
|
||||
clock-output-names: [ '#clock-cells' ]
|
||||
'#clock-cells': [ clock-output-names ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@e0100000 {
|
||||
compatible = "arasan,sdhci-8.9a";
|
||||
reg = <0xe0100000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&clkc 21>, <&clkc 32>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 24 4>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@e2800000 {
|
||||
compatible = "arasan,sdhci-5.1";
|
||||
reg = <0xe2800000 0x1000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&cru 8>, <&cru 18>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 24 4>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3399-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
mmc@fe330000 {
|
||||
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
|
||||
reg = <0xfe330000 0x10000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
arasan,soc-ctl-syscon = <&grf>;
|
||||
assigned-clocks = <&cru SCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clock-output-names = "emmc_cardclock";
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@ff160000 {
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0xff160000 0x1000>;
|
||||
clocks = <&clk200>, <&clk200>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
#clock-cells = <1>;
|
||||
clk-phase-sd-hs = <63>, <72>;
|
||||
};
|
||||
|
||||
- |
|
||||
mmc@f1040000 {
|
||||
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 126 4>;
|
||||
reg = <0xf1040000 0x10000>;
|
||||
clocks = <&clk200>, <&clk200>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
#clock-cells = <1>;
|
||||
clk-phase-sd-hs = <132>, <60>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define LGM_CLK_EMMC5
|
||||
#define LGM_CLK_NGI
|
||||
#define LGM_GCLK_EMMC
|
||||
mmc@ec700000 {
|
||||
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
|
||||
reg = <0xec700000 0x300>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
interrupts = <44 1>;
|
||||
clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
|
||||
<&cgu0 LGM_GCLK_EMMC>;
|
||||
clock-names = "clk_xin", "clk_ahb", "gate";
|
||||
clock-output-names = "emmc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
arasan,soc-ctl-syscon = <&sysconf>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define LGM_CLK_SDIO
|
||||
#define LGM_GCLK_SDXC
|
||||
mmc@ec600000 {
|
||||
compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
|
||||
reg = <0xec600000 0x300>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
interrupts = <43 1>;
|
||||
clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
|
||||
<&cgu0 LGM_GCLK_SDXC>;
|
||||
clock-names = "clk_xin", "clk_ahb", "gate";
|
||||
clock-output-names = "sdxc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
phys = <&sdxc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
arasan,soc-ctl-syscon = <&sysconf>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define KEEM_BAY_PSS_AUX_EMMC
|
||||
#define KEEM_BAY_PSS_EMMC
|
||||
mmc@33000000 {
|
||||
compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x33000000 0x300>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
|
||||
<&scmi_clk KEEM_BAY_PSS_EMMC>;
|
||||
phys = <&emmc_phy>;
|
||||
phy-names = "phy_arasan";
|
||||
assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
clock-output-names = "emmc_cardclock";
|
||||
#clock-cells = <0>;
|
||||
arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
|
||||
};
|
||||
|
||||
- |
|
||||
#define KEEM_BAY_PSS_AUX_SD0
|
||||
#define KEEM_BAY_PSS_SD0
|
||||
mmc@31000000 {
|
||||
compatible = "intel,keembay-sdhci-5.1-sd";
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x31000000 0x300>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
|
||||
<&scmi_clk KEEM_BAY_PSS_SD0>;
|
||||
arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
|
||||
};
|
||||
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