ARM: 5650/1: bcmring: add io.h, uncompress. h, and entry-macro.S
add remaining header files in include/mach directory add entry-macro.S file Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Leo Chen
Russell King
Родитель
3455912574
Коммит
16f5875034
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/*****************************************************************************
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* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/*
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*
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* Low-level IRQ helper macros for BCMRing-based platforms
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*
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*/
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/csp/mm_io.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =(MM_IO_BASE_INTC0)
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ldr \irqstat, [\base, #0] @ get status
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ldr \irqnr, [\base, #0x10] @ mask with enable register
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ands \irqstat, \irqstat, \irqnr
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mov \irqnr, #IRQ_INTC0_START
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cmp \irqstat, #0
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bne 1001f
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ldr \base, =(MM_IO_BASE_INTC1)
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ldr \irqstat, [\base, #0] @ get status
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ldr \irqnr, [\base, #0x10] @ mask with enable register
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ands \irqstat, \irqstat, \irqnr
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mov \irqnr, #IRQ_INTC1_START
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cmp \irqstat, #0
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bne 1001f
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ldr \base, =(MM_IO_BASE_SINTC)
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ldr \irqstat, [\base, #0] @ get status
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ldr \irqnr, [\base, #0x10] @ mask with enable register
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ands \irqstat, \irqstat, \irqnr
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mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
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cmp \irqstat, #0
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beq 1002f
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mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
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1001:
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movs \tmp, \irqstat, lsl #16
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movne \irqstat, \tmp
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addeq \irqnr, \irqnr, #16
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movs \tmp, \irqstat, lsl #8
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movne \irqstat, \tmp
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addeq \irqnr, \irqnr, #8
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movs \tmp, \irqstat, lsl #4
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movne \irqstat, \tmp
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addeq \irqnr, \irqnr, #4
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movs \tmp, \irqstat, lsl #2
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movne \irqstat, \tmp
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addeq \irqnr, \irqnr, #2
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movs \tmp, \irqstat, lsl #1
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addeq \irqnr, \irqnr, #1
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orrs \base, \base, #1
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1002: @ irqnr will be set to 0xffffffff if no irq bits are set
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro irq_prio_table
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.endm
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/*
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*
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* Copyright (C) 1999 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <mach/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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#define __io(a) ((void __iomem *)HW_IO_PHYS_TO_VIRT(a))
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/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */
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/* happen in readw/writew etc. */
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#define readb(c) __raw_readb(c)
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#define readw(c) __raw_readw(c)
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#define readl(c) __raw_readl(c)
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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#define readsb(p, d, l) __raw_readsb(p, d, l)
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#define readsw(p, d, l) __raw_readsw(p, d, l)
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#define readsl(p, d, l) __raw_readsl(p, d, l)
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#define writeb(v, c) __raw_writeb(v, c)
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#define writew(v, c) __raw_writew(v, c)
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#define writel(v, c) __raw_writel(v, c)
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#define writesb(p, d, l) __raw_writesb(p, d, l)
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#define writesw(p, d, l) __raw_writesw(p, d, l)
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#define writesl(p, d, l) __raw_writesl(p, d, l)
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#define memset_io(c, v, l) _memset_io((c), (v), (l))
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#define memcpy_fromio(a, c, l) _memcpy_fromio((a), (c), (l))
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#define memcpy_toio(c, a, l) _memcpy_toio((c), (a), (l))
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#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
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#endif
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@ -0,0 +1,43 @@
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/*****************************************************************************
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* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#include <mach/csp/mm_addr.h>
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#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
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#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
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/*
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* This does not append a newline
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*/
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static inline void putc(int c)
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{
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/* Send out UARTA */
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while (BCMRING_UART_0_FR & (1 << 5))
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;
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BCMRING_UART_0_DR = c;
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}
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static inline void flush(void)
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{
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/* Wait for the tx fifo to be empty */
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while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
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;
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/* Wait for the final character to be sent on the txd line */
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while (BCMRING_UART_0_FR & (1 << 3))
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;
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}
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#define arch_decomp_setup()
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#define arch_decomp_wdog()
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