[MIPS] Make support for weakly ordered LL/SC a config option.
None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
Родитель
ed203dadcd
Коммит
17099b1142
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@ -1190,8 +1190,19 @@ config SYS_HAS_CPU_RM9000
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config SYS_HAS_CPU_SB1
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bool
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#
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# CPU may reorder R->R, R->W, W->R, W->W
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# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
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#
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config WEAK_ORDERING
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bool
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#
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# CPU may reorder reads and writes beyond LL/SC
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# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
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#
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config WEAK_REORDERING_BEYOND_LLSC
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bool
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endmenu
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#
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@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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{
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unsigned long result;
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smp_mb();
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smp_llsc_mb();
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return result;
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}
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@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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* atomic*_return operations are serializing but not the non-*_return
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* versions.
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*/
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#define smp_mb__before_atomic_dec() smp_llsc_mb()
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#define smp_mb__after_atomic_dec() smp_llsc_mb()
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#define smp_mb__before_atomic_inc() smp_llsc_mb()
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#define smp_mb__after_atomic_inc() smp_llsc_mb()
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#include <asm-generic/atomic.h>
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#endif /* _ASM_ATOMIC_H */
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@ -121,6 +121,11 @@
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#else
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#define __WEAK_ORDERING_MB " \n"
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
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#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
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@ -129,4 +134,8 @@
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#define set_mb(var, value) \
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do { var = value; smp_mb(); } while (0)
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#endif /* __ASM_BARRIER_H */
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@ -38,8 +38,8 @@
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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#define smp_mb__before_clear_bit() smp_llsc_mb()
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#define smp_mb__after_clear_bit() smp_llsc_mb()
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/*
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* set_bit - Atomically set a bit in memory
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@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr,
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return res != 0;
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}
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@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return res != 0;
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}
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@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr,
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raw_local_irq_restore(flags);
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}
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smp_mb();
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smp_llsc_mb();
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return res != 0;
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}
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@ -29,7 +29,7 @@
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" .set mips3 \n" \
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"2: sc $1, %2 \n" \
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" beqzl $1, 1b \n" \
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__WEAK_ORDERING_MB \
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__WEAK_LLSC_MB \
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"3: \n" \
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" .set pop \n" \
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" .set mips0 \n" \
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@ -55,7 +55,7 @@
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" .set mips3 \n" \
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"2: sc $1, %2 \n" \
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" beqz $1, 1b \n" \
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__WEAK_ORDERING_MB \
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__WEAK_LLSC_MB \
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"3: \n" \
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" .set pop \n" \
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" .set mips0 \n" \
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@ -152,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
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" .set mips3 \n"
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"2: sc $1, %1 \n"
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" beqzl $1, 1b \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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"3: \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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@ -179,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
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" .set mips3 \n"
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"2: sc $1, %1 \n"
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" beqz $1, 1b \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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"3: \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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@ -67,7 +67,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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: "memory");
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}
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smp_mb();
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smp_llsc_mb();
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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@ -118,7 +118,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
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: "memory");
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}
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smp_mb();
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smp_llsc_mb();
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return res == 0;
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}
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@ -183,7 +183,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
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: "memory");
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}
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smp_mb();
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smp_llsc_mb();
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}
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/* Note the use of sub, not subu which will make the kernel die with an
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@ -193,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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smp_mb();
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smp_llsc_mb();
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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@ -262,7 +262,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
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: "memory");
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}
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smp_mb();
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smp_llsc_mb();
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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@ -293,7 +293,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
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" .set reorder \n"
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" beqzl %1, 1b \n"
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" nop \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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@ -310,7 +310,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
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" beqz %1, 1b \n"
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" nop \n"
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" .set reorder \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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@ -336,7 +336,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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@ -354,7 +354,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
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" beqz %1, 3f \n"
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" li %2, 1 \n"
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"2: \n"
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__WEAK_ORDERING_MB
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__WEAK_LLSC_MB
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" .subsection 2 \n"
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"3: b 1b \n"
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" li %2, 0 \n"
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@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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smp_llsc_mb();
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return retval;
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}
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@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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smp_llsc_mb();
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return retval;
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}
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@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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smp_llsc_mb();
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return retval;
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}
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@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
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raw_local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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smp_llsc_mb();
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return retval;
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}
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