Merge branch 'pm-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus
This commit is contained in:
Tony Lindgren
Коммит
172c113515
|
|
@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
|
|||
obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
|
||||
|
||||
# EMU peripherals
|
||||
obj-$(CONFIG_OMAP3_EMU) += emu.o
|
||||
|
|
|
|||
|
|
@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
|
|||
|
||||
}
|
||||
|
||||
/**
|
||||
* _init_wkdep_usecount - initialize wkdep usecounts to match hardware
|
||||
* @clkdm: clockdomain to initialize wkdep usecounts
|
||||
*
|
||||
* Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
|
||||
* If a wakeup dependency is present in the hardware, the usecount will be
|
||||
* set to 1; otherwise, it will be set to 0. Software should clear all
|
||||
* software wakeup dependencies prior to calling this function if it wishes
|
||||
* to ensure that all usecounts start at 0. No return value.
|
||||
*/
|
||||
static void _init_wkdep_usecount(struct clockdomain *clkdm)
|
||||
{
|
||||
u32 v;
|
||||
struct clkdm_dep *cd;
|
||||
|
||||
if (!clkdm->wkdep_srcs)
|
||||
return;
|
||||
|
||||
for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
|
||||
if (!cd->clkdm && cd->clkdm_name)
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
|
||||
if (!cd->clkdm) {
|
||||
WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
|
||||
"found\n", clkdm->name, cd->clkdm_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
|
||||
PM_WKDEP,
|
||||
(1 << cd->clkdm->dep_bit));
|
||||
|
||||
if (v)
|
||||
pr_debug("clockdomain: %s: wakeup dependency already "
|
||||
"set to wake up when %s wakes\n",
|
||||
clkdm->name, cd->clkdm->name);
|
||||
|
||||
atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
|
||||
* @clkdm: clockdomain to initialize sleepdep usecounts
|
||||
*
|
||||
* Initialize the sleep dependency usecount variables for clockdomain @clkdm.
|
||||
* If a sleep dependency is present in the hardware, the usecount will be
|
||||
* set to 1; otherwise, it will be set to 0. Software should clear all
|
||||
* software sleep dependencies prior to calling this function if it wishes
|
||||
* to ensure that all usecounts start at 0. No return value.
|
||||
*/
|
||||
static void _init_sleepdep_usecount(struct clockdomain *clkdm)
|
||||
{
|
||||
u32 v;
|
||||
struct clkdm_dep *cd;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
return;
|
||||
|
||||
if (!clkdm->sleepdep_srcs)
|
||||
return;
|
||||
|
||||
for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
|
||||
if (!cd->clkdm && cd->clkdm_name)
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
|
||||
if (!cd->clkdm) {
|
||||
WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
|
||||
"not found\n", clkdm->name, cd->clkdm_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
|
||||
OMAP3430_CM_SLEEPDEP,
|
||||
(1 << cd->clkdm->dep_bit));
|
||||
|
||||
if (v)
|
||||
pr_debug("clockdomain: %s: sleep dependency already "
|
||||
"set to prevent from idling until %s "
|
||||
"idles\n", clkdm->name, cd->clkdm->name);
|
||||
|
||||
atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
|
||||
}
|
||||
};
|
||||
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
|
|
@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms,
|
|||
_autodep_lookup(autodep);
|
||||
|
||||
/*
|
||||
* Ensure that the *dep_usecount registers reflect the current
|
||||
* state of the PRCM.
|
||||
* Put all clockdomains into software-supervised mode; PM code
|
||||
* should later enable hardware-supervised mode as appropriate
|
||||
*/
|
||||
list_for_each_entry(clkdm, &clkdm_list, node) {
|
||||
_init_wkdep_usecount(clkdm);
|
||||
_init_sleepdep_usecount(clkdm);
|
||||
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
|
||||
omap2_clkdm_wakeup(clkdm);
|
||||
else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
|
||||
omap2_clkdm_deny_idle(clkdm);
|
||||
|
||||
clkdm_clear_all_wkdeps(clkdm);
|
||||
clkdm_clear_all_sleepdeps(clkdm);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
|
|||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
|
||||
if (!cd->clkdm && cd->clkdm_name)
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
|
||||
/* PRM accesses are slow, so minimize them */
|
||||
mask |= 1 << cd->clkdm->dep_bit;
|
||||
atomic_set(&cd->wkdep_usecount, 0);
|
||||
|
|
@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
|
|||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
|
||||
if (!cd->clkdm && cd->clkdm_name)
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
|
||||
/* PRM accesses are slow, so minimize them */
|
||||
mask |= 1 << cd->clkdm->dep_bit;
|
||||
atomic_set(&cd->sleepdep_usecount, 0);
|
||||
|
|
|
|||
|
|
@ -60,7 +60,8 @@ struct omap3_processor_cx {
|
|||
|
||||
struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
|
||||
struct omap3_processor_cx current_cx_state;
|
||||
struct powerdomain *mpu_pd, *core_pd;
|
||||
struct powerdomain *mpu_pd, *core_pd, *per_pd;
|
||||
struct powerdomain *cam_pd;
|
||||
|
||||
/*
|
||||
* The latencies/thresholds for various C states have
|
||||
|
|
@ -233,14 +234,62 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
|||
struct cpuidle_state *state)
|
||||
{
|
||||
struct cpuidle_state *new_state = next_valid_state(dev, state);
|
||||
u32 core_next_state, per_next_state = 0, per_saved_state = 0;
|
||||
u32 cam_state;
|
||||
struct omap3_processor_cx *cx;
|
||||
int ret;
|
||||
|
||||
if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
|
||||
BUG_ON(!dev->safe_state);
|
||||
new_state = dev->safe_state;
|
||||
goto select_state;
|
||||
}
|
||||
|
||||
cx = cpuidle_get_statedata(state);
|
||||
core_next_state = cx->core_state;
|
||||
|
||||
/*
|
||||
* FIXME: we currently manage device-specific idle states
|
||||
* for PER and CORE in combination with CPU-specific
|
||||
* idle states. This is wrong, and device-specific
|
||||
* idle managment needs to be separated out into
|
||||
* its own code.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Prevent idle completely if CAM is active.
|
||||
* CAM does not have wakeup capability in OMAP3.
|
||||
*/
|
||||
cam_state = pwrdm_read_pwrst(cam_pd);
|
||||
if (cam_state == PWRDM_POWER_ON) {
|
||||
new_state = dev->safe_state;
|
||||
goto select_state;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent PER off if CORE is not in retention or off as this
|
||||
* would disable PER wakeups completely.
|
||||
*/
|
||||
per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
|
||||
if ((per_next_state == PWRDM_POWER_OFF) &&
|
||||
(core_next_state > PWRDM_POWER_RET)) {
|
||||
per_next_state = PWRDM_POWER_RET;
|
||||
pwrdm_set_next_pwrst(per_pd, per_next_state);
|
||||
}
|
||||
|
||||
/* Are we changing PER target state? */
|
||||
if (per_next_state != per_saved_state)
|
||||
pwrdm_set_next_pwrst(per_pd, per_next_state);
|
||||
|
||||
select_state:
|
||||
dev->last_state = new_state;
|
||||
return omap3_enter_idle(dev, new_state);
|
||||
ret = omap3_enter_idle(dev, new_state);
|
||||
|
||||
/* Restore original PER state if it was modified */
|
||||
if (per_next_state != per_saved_state)
|
||||
pwrdm_set_next_pwrst(per_pd, per_saved_state);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
|
||||
|
|
@ -328,7 +377,8 @@ void omap_init_power_states(void)
|
|||
cpuidle_params_table[OMAP3_STATE_C2].threshold;
|
||||
omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
|
||||
omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
|
||||
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
|
||||
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
|
||||
CPUIDLE_FLAG_CHECK_BM;
|
||||
|
||||
/* C3 . MPU CSWR + Core inactive */
|
||||
omap3_power_states[OMAP3_STATE_C3].valid =
|
||||
|
|
@ -426,6 +476,8 @@ int __init omap3_idle_init(void)
|
|||
|
||||
mpu_pd = pwrdm_lookup("mpu_pwrdm");
|
||||
core_pd = pwrdm_lookup("core_pwrdm");
|
||||
per_pd = pwrdm_lookup("per_pwrdm");
|
||||
cam_pd = pwrdm_lookup("cam_pwrdm");
|
||||
|
||||
omap_init_power_states();
|
||||
cpuidle_register_driver(&omap3_idle_driver);
|
||||
|
|
|
|||
|
|
@ -323,6 +323,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
|||
omap2430_hwmod_init();
|
||||
else if (cpu_is_omap34xx())
|
||||
omap3xxx_hwmod_init();
|
||||
else if (cpu_is_omap44xx())
|
||||
omap44xx_hwmod_init();
|
||||
|
||||
/* The OPP tables have to be registered before a clk init */
|
||||
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
|
||||
|
||||
|
|
@ -342,9 +345,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
|||
#ifndef CONFIG_PM_RUNTIME
|
||||
skip_setup_idle = 1;
|
||||
#endif
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
|
||||
omap_hwmod_late_init(skip_setup_idle);
|
||||
|
||||
omap_hwmod_late_init(skip_setup_idle);
|
||||
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
||||
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
||||
_omap2_init_reprogram_sdrc();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,482 @@
|
|||
/*
|
||||
* Hardware modules present on the OMAP44xx chips
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley
|
||||
* Benoit Cousson
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
#include "cm.h"
|
||||
#include "prm-regbits-44xx.h"
|
||||
|
||||
/* Base offset for all OMAP4 interrupts external to MPUSS */
|
||||
#define OMAP44XX_IRQ_GIC_START 32
|
||||
|
||||
/* Base offset for all OMAP4 dma requests */
|
||||
#define OMAP44XX_DMA_REQ_START 1
|
||||
|
||||
/* Backward references (IPs with Bus Master capability) */
|
||||
static struct omap_hwmod omap44xx_dmm_hwmod;
|
||||
static struct omap_hwmod omap44xx_emif_fw_hwmod;
|
||||
static struct omap_hwmod omap44xx_l3_instr_hwmod;
|
||||
static struct omap_hwmod omap44xx_l3_main_1_hwmod;
|
||||
static struct omap_hwmod omap44xx_l3_main_2_hwmod;
|
||||
static struct omap_hwmod omap44xx_l3_main_3_hwmod;
|
||||
static struct omap_hwmod omap44xx_l4_abe_hwmod;
|
||||
static struct omap_hwmod omap44xx_l4_cfg_hwmod;
|
||||
static struct omap_hwmod omap44xx_l4_per_hwmod;
|
||||
static struct omap_hwmod omap44xx_l4_wkup_hwmod;
|
||||
static struct omap_hwmod omap44xx_mpu_hwmod;
|
||||
static struct omap_hwmod omap44xx_mpu_private_hwmod;
|
||||
|
||||
/*
|
||||
* Interconnects omap_hwmod structures
|
||||
* hwmods that compose the global OMAP interconnect
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'dmm' class
|
||||
* instance(s): dmm
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
|
||||
.name = "dmm",
|
||||
};
|
||||
|
||||
/* dmm interface data */
|
||||
/* l3_main_1 -> dmm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_dmm_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> dmm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_dmm_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dmm slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
|
||||
&omap44xx_l3_main_1__dmm,
|
||||
&omap44xx_mpu__dmm,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
|
||||
{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dmm_hwmod = {
|
||||
.name = "dmm",
|
||||
.class = &omap44xx_dmm_hwmod_class,
|
||||
.slaves = omap44xx_dmm_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
|
||||
.mpu_irqs = omap44xx_dmm_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'emif_fw' class
|
||||
* instance(s): emif_fw
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
|
||||
.name = "emif_fw",
|
||||
};
|
||||
|
||||
/* emif_fw interface data */
|
||||
/* dmm -> emif_fw */
|
||||
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
|
||||
.master = &omap44xx_dmm_hwmod,
|
||||
.slave = &omap44xx_emif_fw_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> emif_fw */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_emif_fw_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* emif_fw slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
|
||||
&omap44xx_dmm__emif_fw,
|
||||
&omap44xx_l4_cfg__emif_fw,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_emif_fw_hwmod = {
|
||||
.name = "emif_fw",
|
||||
.class = &omap44xx_emif_fw_hwmod_class,
|
||||
.slaves = omap44xx_emif_fw_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l3' class
|
||||
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
|
||||
.name = "l3",
|
||||
};
|
||||
|
||||
/* l3_instr interface data */
|
||||
/* l3_main_3 -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
|
||||
.master = &omap44xx_l3_main_3_hwmod,
|
||||
.slave = &omap44xx_l3_instr_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_instr slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
|
||||
&omap44xx_l3_main_3__l3_instr,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l3_instr_hwmod = {
|
||||
.name = "l3_instr",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.slaves = omap44xx_l3_instr_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> l3_main_1 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_l3_main_1_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
|
||||
&omap44xx_l3_main_2__l3_main_1,
|
||||
&omap44xx_l4_cfg__l3_main_1,
|
||||
&omap44xx_mpu__l3_main_1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
|
||||
.name = "l3_main_1",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.slaves = omap44xx_l3_main_1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_2 interface data */
|
||||
/* l3_main_1 -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
|
||||
&omap44xx_l3_main_1__l3_main_2,
|
||||
&omap44xx_l4_cfg__l3_main_2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
|
||||
.name = "l3_main_2",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.slaves = omap44xx_l3_main_2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_3 interface data */
|
||||
/* l3_main_1 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_3 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l3_main_3_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_3 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
|
||||
&omap44xx_l3_main_1__l3_main_3,
|
||||
&omap44xx_l3_main_2__l3_main_3,
|
||||
&omap44xx_l4_cfg__l3_main_3,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
|
||||
.name = "l3_main_3",
|
||||
.class = &omap44xx_l3_hwmod_class,
|
||||
.slaves = omap44xx_l3_main_3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'l4' class
|
||||
* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
|
||||
.name = "l4",
|
||||
};
|
||||
|
||||
/* l4_abe interface data */
|
||||
/* l3_main_1 -> l4_abe */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l4_abe_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu -> l4_abe */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_l4_abe_hwmod,
|
||||
.clk = "ocp_abe_iclk",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_abe slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
|
||||
&omap44xx_l3_main_1__l4_abe,
|
||||
&omap44xx_mpu__l4_abe,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l4_abe_hwmod = {
|
||||
.name = "l4_abe",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.slaves = omap44xx_l4_abe_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_cfg interface data */
|
||||
/* l3_main_1 -> l4_cfg */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
.slave = &omap44xx_l4_cfg_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
|
||||
&omap44xx_l3_main_1__l4_cfg,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
|
||||
.name = "l4_cfg",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.slaves = omap44xx_l4_cfg_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_per interface data */
|
||||
/* l3_main_2 -> l4_per */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_l4_per_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_per slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
|
||||
&omap44xx_l3_main_2__l4_per,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l4_per_hwmod = {
|
||||
.name = "l4_per",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.slaves = omap44xx_l4_per_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_wkup interface data */
|
||||
/* l4_cfg -> l4_wkup */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_l4_wkup_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
|
||||
&omap44xx_l4_cfg__l4_wkup,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &omap44xx_l4_hwmod_class,
|
||||
.slaves = omap44xx_l4_wkup_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu_bus' class
|
||||
* instance(s): mpu_private
|
||||
*/
|
||||
static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
|
||||
.name = "mpu_bus",
|
||||
};
|
||||
|
||||
/* mpu_private interface data */
|
||||
/* mpu -> mpu_private */
|
||||
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
|
||||
.master = &omap44xx_mpu_hwmod,
|
||||
.slave = &omap44xx_mpu_private_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* mpu_private slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
|
||||
&omap44xx_mpu__mpu_private,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
|
||||
.name = "mpu_private",
|
||||
.class = &omap44xx_mpu_bus_hwmod_class,
|
||||
.slaves = omap44xx_mpu_private_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
* mpu sub-system
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
|
||||
.name = "mpu",
|
||||
};
|
||||
|
||||
/* mpu */
|
||||
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
|
||||
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
|
||||
};
|
||||
|
||||
/* mpu master ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
|
||||
&omap44xx_mpu__l3_main_1,
|
||||
&omap44xx_mpu__l4_abe,
|
||||
&omap44xx_mpu__dmm,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &omap44xx_mpu_hwmod_class,
|
||||
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
|
||||
.mpu_irqs = omap44xx_mpu_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
|
||||
.main_clk = "dpll_mpu_m2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
|
||||
},
|
||||
},
|
||||
.masters = omap44xx_mpu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
||||
/* dmm class */
|
||||
&omap44xx_dmm_hwmod,
|
||||
/* emif_fw class */
|
||||
&omap44xx_emif_fw_hwmod,
|
||||
/* l3 class */
|
||||
&omap44xx_l3_instr_hwmod,
|
||||
&omap44xx_l3_main_1_hwmod,
|
||||
&omap44xx_l3_main_2_hwmod,
|
||||
&omap44xx_l3_main_3_hwmod,
|
||||
/* l4 class */
|
||||
&omap44xx_l4_abe_hwmod,
|
||||
&omap44xx_l4_cfg_hwmod,
|
||||
&omap44xx_l4_per_hwmod,
|
||||
&omap44xx_l4_wkup_hwmod,
|
||||
/* mpu_bus class */
|
||||
&omap44xx_mpu_private_hwmod,
|
||||
|
||||
/* mpu class */
|
||||
&omap44xx_mpu_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init omap44xx_hwmod_init(void)
|
||||
{
|
||||
return omap_hwmod_init(omap44xx_hwmods);
|
||||
}
|
||||
|
||||
|
|
@ -31,12 +31,17 @@
|
|||
#include <plat/board.h>
|
||||
#include <plat/powerdomain.h>
|
||||
#include <plat/clockdomain.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "prm.h"
|
||||
#include "cm.h"
|
||||
#include "pm.h"
|
||||
|
||||
int omap2_pm_debug;
|
||||
u32 enable_off_mode;
|
||||
u32 sleep_while_idle;
|
||||
u32 wakeup_timer_seconds;
|
||||
u32 wakeup_timer_milliseconds;
|
||||
|
||||
#define DUMP_PRM_MOD_REG(mod, reg) \
|
||||
regs[reg_count].name = #mod "." #reg; \
|
||||
|
|
@ -349,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
|
|||
pwrdm->timer = t;
|
||||
}
|
||||
|
||||
void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
|
||||
{
|
||||
u32 tick_rate, cycles;
|
||||
|
||||
if (!seconds && !milliseconds)
|
||||
return;
|
||||
|
||||
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
|
||||
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
|
||||
omap_dm_timer_stop(gptimer_wakeup);
|
||||
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
|
||||
|
||||
pr_info("PM: Resume timer in %u.%03u secs"
|
||||
" (%d ticks at %d ticks/sec.)\n",
|
||||
seconds, milliseconds, cycles, tick_rate);
|
||||
}
|
||||
|
||||
static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
|
||||
{
|
||||
struct seq_file *s = (struct seq_file *)user;
|
||||
|
|
@ -494,8 +516,10 @@ int pm_dbg_regset_init(int reg_set)
|
|||
|
||||
static int pwrdm_suspend_get(void *data, u64 *val)
|
||||
{
|
||||
int ret;
|
||||
ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (cpu_is_omap34xx())
|
||||
ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
|
||||
*val = ret;
|
||||
|
||||
if (ret >= 0)
|
||||
|
|
@ -505,7 +529,10 @@ static int pwrdm_suspend_get(void *data, u64 *val)
|
|||
|
||||
static int pwrdm_suspend_set(void *data, u64 val)
|
||||
{
|
||||
return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
|
||||
if (cpu_is_omap34xx())
|
||||
return omap3_pm_set_suspend_state(
|
||||
(struct powerdomain *)data, (int)val);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
|
||||
|
|
@ -553,8 +580,10 @@ static int option_set(void *data, u64 val)
|
|||
|
||||
*option = val;
|
||||
|
||||
if (option == &enable_off_mode)
|
||||
omap3_pm_off_mode_enable(val);
|
||||
if (option == &enable_off_mode) {
|
||||
if (cpu_is_omap34xx())
|
||||
omap3_pm_off_mode_enable(val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -609,6 +638,9 @@ static int __init pm_dbg_init(void)
|
|||
&sleep_while_idle, &pm_dbg_option_fops);
|
||||
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
|
||||
&wakeup_timer_seconds, &pm_dbg_option_fops);
|
||||
(void) debugfs_create_file("wakeup_timer_milliseconds",
|
||||
S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
|
||||
&pm_dbg_option_fops);
|
||||
pm_dbg_init_done = 1;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -18,11 +18,15 @@
|
|||
#include <plat/omap_device.h>
|
||||
#include <plat/common.h>
|
||||
|
||||
#include <plat/powerdomain.h>
|
||||
#include <plat/clockdomain.h>
|
||||
|
||||
static struct omap_device_pm_latency *pm_lats;
|
||||
|
||||
static struct device *mpu_dev;
|
||||
static struct device *dsp_dev;
|
||||
static struct device *iva_dev;
|
||||
static struct device *l3_dev;
|
||||
static struct device *dsp_dev;
|
||||
|
||||
struct device *omap2_get_mpuss_device(void)
|
||||
{
|
||||
|
|
@ -30,10 +34,10 @@ struct device *omap2_get_mpuss_device(void)
|
|||
return mpu_dev;
|
||||
}
|
||||
|
||||
struct device *omap2_get_dsp_device(void)
|
||||
struct device *omap2_get_iva_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!dsp_dev);
|
||||
return dsp_dev;
|
||||
WARN_ON_ONCE(!iva_dev);
|
||||
return iva_dev;
|
||||
}
|
||||
|
||||
struct device *omap2_get_l3_device(void)
|
||||
|
|
@ -42,6 +46,13 @@ struct device *omap2_get_l3_device(void)
|
|||
return l3_dev;
|
||||
}
|
||||
|
||||
struct device *omap4_get_dsp_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!dsp_dev);
|
||||
return dsp_dev;
|
||||
}
|
||||
EXPORT_SYMBOL(omap4_get_dsp_device);
|
||||
|
||||
/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
|
||||
static int _init_omap_device(char *name, struct device **new_dev)
|
||||
{
|
||||
|
|
@ -69,8 +80,60 @@ static int _init_omap_device(char *name, struct device **new_dev)
|
|||
static void omap2_init_processor_devices(void)
|
||||
{
|
||||
_init_omap_device("mpu", &mpu_dev);
|
||||
_init_omap_device("iva", &dsp_dev);
|
||||
_init_omap_device("l3_main", &l3_dev);
|
||||
_init_omap_device("iva", &iva_dev);
|
||||
if (cpu_is_omap44xx()) {
|
||||
_init_omap_device("l3_main_1", &l3_dev);
|
||||
_init_omap_device("dsp", &dsp_dev);
|
||||
} else {
|
||||
_init_omap_device("l3_main", &l3_dev);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This sets pwrdm state (other than mpu & core. Currently only ON &
|
||||
* RET are supported. Function is assuming that clkdm doesn't have
|
||||
* hw_sup mode enabled.
|
||||
*/
|
||||
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
||||
{
|
||||
u32 cur_state;
|
||||
int sleep_switch = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (pwrdm == NULL || IS_ERR(pwrdm))
|
||||
return -EINVAL;
|
||||
|
||||
while (!(pwrdm->pwrsts & (1 << state))) {
|
||||
if (state == PWRDM_POWER_OFF)
|
||||
return ret;
|
||||
state--;
|
||||
}
|
||||
|
||||
cur_state = pwrdm_read_next_pwrst(pwrdm);
|
||||
if (cur_state == state)
|
||||
return ret;
|
||||
|
||||
if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
|
||||
omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
||||
sleep_switch = 1;
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
}
|
||||
|
||||
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
||||
pwrdm->name);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (sleep_switch) {
|
||||
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
pwrdm_state_switch(pwrdm);
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init omap2_common_pm_init(void)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ extern void *omap3_secure_ram_storage;
|
|||
extern void omap3_pm_off_mode_enable(int);
|
||||
extern void omap_sram_idle(void);
|
||||
extern int omap3_can_sleep(void);
|
||||
extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
|
||||
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
|
||||
extern int omap3_idle_init(void);
|
||||
|
||||
struct cpuidle_params {
|
||||
|
|
@ -48,9 +48,11 @@ extern struct omap_dm_timer *gptimer_wakeup;
|
|||
|
||||
#ifdef CONFIG_PM_DEBUG
|
||||
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
|
||||
extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
|
||||
extern int omap2_pm_debug;
|
||||
#else
|
||||
#define omap2_pm_dump(mode, resume, us) do {} while (0);
|
||||
#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
|
||||
#define omap2_pm_debug 0
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@
|
|||
#include <plat/prcm.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
|
|
@ -55,11 +54,6 @@
|
|||
#define OMAP343X_TABLE_VALUE_OFFSET 0x30
|
||||
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
|
||||
|
||||
u32 enable_off_mode;
|
||||
u32 sleep_while_idle;
|
||||
u32 wakeup_timer_seconds;
|
||||
u32 wakeup_timer_milliseconds;
|
||||
|
||||
struct power_state {
|
||||
struct powerdomain *pwrdm;
|
||||
u32 next_state;
|
||||
|
|
@ -351,7 +345,6 @@ void omap_sram_idle(void)
|
|||
int core_next_state = PWRDM_POWER_ON;
|
||||
int core_prev_state, per_prev_state;
|
||||
u32 sdrc_pwr = 0;
|
||||
int per_state_modified = 0;
|
||||
|
||||
if (!_omap_sram_idle)
|
||||
return;
|
||||
|
|
@ -385,9 +378,9 @@ void omap_sram_idle(void)
|
|||
/* Enable IO-PAD and IO-CHAIN wakeups */
|
||||
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
|
||||
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
|
||||
if (omap3_has_io_wakeup() && \
|
||||
(per_next_state < PWRDM_POWER_ON ||
|
||||
core_next_state < PWRDM_POWER_ON)) {
|
||||
if (omap3_has_io_wakeup() &&
|
||||
(per_next_state < PWRDM_POWER_ON ||
|
||||
core_next_state < PWRDM_POWER_ON)) {
|
||||
prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
|
||||
omap3_enable_io_chain();
|
||||
}
|
||||
|
|
@ -396,19 +389,10 @@ void omap_sram_idle(void)
|
|||
if (per_next_state < PWRDM_POWER_ON) {
|
||||
omap_uart_prepare_idle(2);
|
||||
omap2_gpio_prepare_for_idle(per_next_state);
|
||||
if (per_next_state == PWRDM_POWER_OFF) {
|
||||
if (core_next_state == PWRDM_POWER_ON) {
|
||||
per_next_state = PWRDM_POWER_RET;
|
||||
pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
|
||||
per_state_modified = 1;
|
||||
} else
|
||||
if (per_next_state == PWRDM_POWER_OFF)
|
||||
omap3_per_save_context();
|
||||
}
|
||||
}
|
||||
|
||||
if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
|
||||
omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
|
||||
|
||||
/* CORE */
|
||||
if (core_next_state < PWRDM_POWER_ON) {
|
||||
omap_uart_prepare_idle(0);
|
||||
|
|
@ -475,8 +459,6 @@ void omap_sram_idle(void)
|
|||
if (per_prev_state == PWRDM_POWER_OFF)
|
||||
omap3_per_restore_context();
|
||||
omap_uart_resume_idle(2);
|
||||
if (per_state_modified)
|
||||
pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
|
||||
}
|
||||
|
||||
/* Disable IO-PAD and IO-CHAIN wakeup */
|
||||
|
|
@ -501,51 +483,6 @@ int omap3_can_sleep(void)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* This sets pwrdm state (other than mpu & core. Currently only ON &
|
||||
* RET are supported. Function is assuming that clkdm doesn't have
|
||||
* hw_sup mode enabled. */
|
||||
int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
||||
{
|
||||
u32 cur_state;
|
||||
int sleep_switch = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (pwrdm == NULL || IS_ERR(pwrdm))
|
||||
return -EINVAL;
|
||||
|
||||
while (!(pwrdm->pwrsts & (1 << state))) {
|
||||
if (state == PWRDM_POWER_OFF)
|
||||
return ret;
|
||||
state--;
|
||||
}
|
||||
|
||||
cur_state = pwrdm_read_next_pwrst(pwrdm);
|
||||
if (cur_state == state)
|
||||
return ret;
|
||||
|
||||
if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
|
||||
omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
||||
sleep_switch = 1;
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
}
|
||||
|
||||
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
||||
pwrdm->name);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (sleep_switch) {
|
||||
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
pwrdm_state_switch(pwrdm);
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap3_pm_idle(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
|
|
@ -567,23 +504,6 @@ out:
|
|||
#ifdef CONFIG_SUSPEND
|
||||
static suspend_state_t suspend_state;
|
||||
|
||||
static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
|
||||
{
|
||||
u32 tick_rate, cycles;
|
||||
|
||||
if (!seconds && !milliseconds)
|
||||
return;
|
||||
|
||||
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
|
||||
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
|
||||
omap_dm_timer_stop(gptimer_wakeup);
|
||||
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
|
||||
|
||||
pr_info("PM: Resume timer in %u.%03u secs"
|
||||
" (%d ticks at %d ticks/sec.)\n",
|
||||
seconds, milliseconds, cycles, tick_rate);
|
||||
}
|
||||
|
||||
static int omap3_pm_prepare(void)
|
||||
{
|
||||
disable_hlt();
|
||||
|
|
@ -604,7 +524,7 @@ static int omap3_pm_suspend(void)
|
|||
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
|
||||
/* Set ones wanted by suspend */
|
||||
list_for_each_entry(pwrst, &pwrst_list, node) {
|
||||
if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
||||
if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
||||
goto restore;
|
||||
if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
|
||||
goto restore;
|
||||
|
|
@ -625,7 +545,7 @@ restore:
|
|||
pwrst->pwrdm->name, pwrst->next_state);
|
||||
ret = -1;
|
||||
}
|
||||
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
||||
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
||||
}
|
||||
if (ret)
|
||||
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
|
||||
|
|
@ -974,7 +894,7 @@ void omap3_pm_off_mode_enable(int enable)
|
|||
|
||||
list_for_each_entry(pwrst, &pwrst_list, node) {
|
||||
pwrst->next_state = state;
|
||||
set_pwrdm_state(pwrst->pwrdm, state);
|
||||
omap_set_pwrdm_state(pwrst->pwrdm, state);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1019,7 +939,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
|||
if (pwrdm_has_hdwr_sar(pwrdm))
|
||||
pwrdm_enable_hdwr_sar(pwrdm);
|
||||
|
||||
return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
||||
return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1029,9 +949,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
|||
*/
|
||||
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
|
||||
{
|
||||
clkdm_clear_all_wkdeps(clkdm);
|
||||
clkdm_clear_all_sleepdeps(clkdm);
|
||||
|
||||
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
|
||||
omap2_clkdm_allow_idle(clkdm);
|
||||
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
|
||||
|
|
|
|||
|
|
@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
|
|||
# OMAP mailbox framework
|
||||
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
|
||||
|
||||
obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
|
||||
obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
|
||||
|
|
|
|||
|
|
@ -2085,8 +2085,9 @@ void omap2_gpio_prepare_for_idle(int power_state)
|
|||
for (i = min; i < gpio_bank_count; i++) {
|
||||
struct gpio_bank *bank = &gpio_bank[i];
|
||||
u32 l1, l2;
|
||||
int j;
|
||||
|
||||
if (bank->dbck_enable_mask)
|
||||
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
||||
clk_disable(bank->dbck);
|
||||
|
||||
if (power_state > PWRDM_POWER_OFF)
|
||||
|
|
@ -2152,8 +2153,9 @@ void omap2_gpio_resume_after_idle(void)
|
|||
for (i = min; i < gpio_bank_count; i++) {
|
||||
struct gpio_bank *bank = &gpio_bank[i];
|
||||
u32 l, gen, gen0, gen1;
|
||||
int j;
|
||||
|
||||
if (bank->dbck_enable_mask)
|
||||
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
||||
clk_enable(bank->dbck);
|
||||
|
||||
if (!workaround_enabled)
|
||||
|
|
|
|||
|
|
@ -91,7 +91,8 @@ void omap3_map_io(void);
|
|||
})
|
||||
|
||||
extern struct device *omap2_get_mpuss_device(void);
|
||||
extern struct device *omap2_get_dsp_device(void);
|
||||
extern struct device *omap2_get_iva_device(void);
|
||||
extern struct device *omap2_get_l3_device(void);
|
||||
extern struct device *omap4_get_dsp_device(void);
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
extern struct device omap_device_parent;
|
||||
|
||||
/* omap_device._state values */
|
||||
#define OMAP_DEVICE_STATE_UNKNOWN 0
|
||||
#define OMAP_DEVICE_STATE_ENABLED 1
|
||||
|
|
@ -62,7 +64,6 @@
|
|||
*
|
||||
*/
|
||||
struct omap_device {
|
||||
u32 magic;
|
||||
struct platform_device pdev;
|
||||
struct omap_hwmod **hwmods;
|
||||
struct omap_device_pm_latency *pm_lats;
|
||||
|
|
@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
|
|||
|
||||
/* Core code interface */
|
||||
|
||||
bool omap_device_is_valid(struct omap_device *od);
|
||||
int omap_device_count_resources(struct omap_device *od);
|
||||
int omap_device_fill_resources(struct omap_device *od, struct resource *res);
|
||||
|
||||
|
|
|
|||
|
|
@ -561,5 +561,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
|
|||
extern int omap2420_hwmod_init(void);
|
||||
extern int omap2430_hwmod_init(void);
|
||||
extern int omap3xxx_hwmod_init(void);
|
||||
extern int omap44xx_hwmod_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -91,12 +91,6 @@
|
|||
#define USE_WAKEUP_LAT 0
|
||||
#define IGNORE_WAKEUP_LAT 1
|
||||
|
||||
/*
|
||||
* OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
|
||||
* obtained via container_of() is in fact a struct omap_device
|
||||
*/
|
||||
#define OMAP_DEVICE_MAGIC 0xf00dcafe
|
||||
|
||||
/* Private functions */
|
||||
|
||||
/**
|
||||
|
|
@ -453,8 +447,6 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
|
|||
od->pm_lats = pm_lats;
|
||||
od->pm_lats_cnt = pm_lats_cnt;
|
||||
|
||||
od->magic = OMAP_DEVICE_MAGIC;
|
||||
|
||||
if (is_early_device)
|
||||
ret = omap_early_device_register(od);
|
||||
else
|
||||
|
|
@ -514,6 +506,7 @@ int omap_device_register(struct omap_device *od)
|
|||
{
|
||||
pr_debug("omap_device: %s: registering\n", od->pdev.name);
|
||||
|
||||
od->pdev.dev.parent = &omap_device_parent;
|
||||
return platform_device_register(&od->pdev);
|
||||
}
|
||||
|
||||
|
|
@ -667,18 +660,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_device_is_valid - Check if pointer is a valid omap_device
|
||||
* @od: struct omap_device *
|
||||
*
|
||||
* Return whether struct omap_device pointer @od points to a valid
|
||||
* omap_device.
|
||||
*/
|
||||
bool omap_device_is_valid(struct omap_device *od)
|
||||
{
|
||||
return (od && od->magic == OMAP_DEVICE_MAGIC);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_device_get_pwrdm - return the powerdomain * associated with @od
|
||||
* @od: struct omap_device *
|
||||
|
|
@ -798,3 +779,14 @@ int omap_device_enable_clocks(struct omap_device *od)
|
|||
/* XXX pass along return value here? */
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct device omap_device_parent = {
|
||||
.init_name = "omap",
|
||||
.parent = &platform_bus,
|
||||
};
|
||||
|
||||
static int __init omap_device_init(void)
|
||||
{
|
||||
return device_register(&omap_device_parent);
|
||||
}
|
||||
core_initcall(omap_device_init);
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче