iwlwifi: fix the delta for remove max_txq_num patch
BIg portion of "iwlwifi: remove max_txq_num from hw_params" was missing during merge, here is the fix for it. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Родитель
9ba1947a89
Коммит
1745e4405b
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@ -122,8 +122,6 @@ static const struct iwl_sensitivity_ranges iwl1000_sensitivity = {
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static void iwl1000_hw_set_hw_params(struct iwl_priv *priv)
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{
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hw_params(priv).max_txq_num = cfg(priv)->base_params->num_of_queues;
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hw_params(priv).ht40_channel = BIT(IEEE80211_BAND_2GHZ);
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hw_params(priv).tx_chains_num =
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@ -117,8 +117,6 @@ static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {
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static void iwl2000_hw_set_hw_params(struct iwl_priv *priv)
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{
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hw_params(priv).max_txq_num = cfg(priv)->base_params->num_of_queues;
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hw_params(priv).ht40_channel = BIT(IEEE80211_BAND_2GHZ);
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hw_params(priv).tx_chains_num =
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@ -156,8 +156,6 @@ static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
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static void iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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{
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hw_params(priv).max_txq_num = cfg(priv)->base_params->num_of_queues;
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hw_params(priv).ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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@ -174,8 +172,6 @@ static void iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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static void iwl5150_hw_set_hw_params(struct iwl_priv *priv)
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{
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hw_params(priv).max_txq_num = cfg(priv)->base_params->num_of_queues;
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hw_params(priv).ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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@ -139,8 +139,6 @@ static const struct iwl_sensitivity_ranges iwl6000_sensitivity = {
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static void iwl6000_hw_set_hw_params(struct iwl_priv *priv)
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{
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hw_params(priv).max_txq_num = cfg(priv)->base_params->num_of_queues;
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hw_params(priv).ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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@ -1159,7 +1159,7 @@ int iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
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* (in Tx queue's circular buffer) of first TFD/frame in window */
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u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
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if (scd_flow >= hw_params(priv).max_txq_num) {
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if (scd_flow >= cfg(priv)->base_params->num_of_queues) {
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IWL_ERR(priv,
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"BUG_ON scd_flow is bigger than number of queues\n");
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return 0;
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@ -828,7 +828,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
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char *buf;
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int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
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(hw_params(priv).max_txq_num * 32 * 8) + 400;
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(cfg(priv)->base_params->num_of_queues * 32 * 8) + 400;
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const u8 *ptr;
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ssize_t ret;
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@ -160,7 +160,6 @@ struct iwl_mod_params {
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*
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* Holds the module parameters
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*
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* @max_txq_num: Max # Tx queues supported
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* @num_ampdu_queues: num of ampdu queues
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* @tx_chains_num: Number of TX chains
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* @rx_chains_num: Number of RX chains
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@ -177,7 +176,6 @@ struct iwl_mod_params {
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* @use_rts_for_aggregation: use rts/cts protection for HT traffic
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*/
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struct iwl_hw_params {
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u8 max_txq_num;
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u8 num_ampdu_queues;
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u8 tx_chains_num;
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u8 rx_chains_num;
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@ -1050,7 +1050,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
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if (inta & CSR_INT_BIT_WAKEUP) {
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IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
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iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
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for (i = 0; i < hw_params(trans).max_txq_num; i++)
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for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++)
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iwl_txq_update_write_ptr(trans,
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&trans_pcie->txq[i]);
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@ -595,7 +595,8 @@ static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int txq_id;
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for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
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for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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txq_id++)
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if (!test_and_set_bit(txq_id,
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&trans_pcie->txq_ctx_active_msk))
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return txq_id;
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@ -497,7 +497,7 @@ static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
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/* Tx queues */
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if (trans_pcie->txq) {
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for (txq_id = 0;
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txq_id < hw_params(trans).max_txq_num; txq_id++)
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txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
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iwl_tx_queue_free(trans, txq_id);
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}
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@ -522,7 +522,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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int txq_id, slots_num;
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
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u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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/*It is not allowed to alloc twice, so warn when this happens.
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@ -546,7 +546,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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goto error;
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}
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trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
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trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
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sizeof(struct iwl_tx_queue), GFP_KERNEL);
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if (!trans_pcie->txq) {
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IWL_ERR(trans, "Not enough memory for txq\n");
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@ -555,7 +555,8 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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}
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
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for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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txq_id++) {
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slots_num = (txq_id == trans_pcie->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
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@ -600,7 +601,8 @@ static int iwl_tx_init(struct iwl_trans *trans)
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
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for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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txq_id++) {
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slots_num = (txq_id == trans_pcie->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
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@ -1116,7 +1118,8 @@ static void iwl_tx_start(struct iwl_trans *trans)
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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for (; a < trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
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SCD_TRANS_TBL_OFFSET_QUEUE(
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cfg(trans)->base_params->num_of_queues);
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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@ -1139,7 +1142,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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iwl_write_prph(trans, SCD_AGGR_SEL, 0);
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/* initiate the queues */
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for (i = 0; i < hw_params(trans).max_txq_num; i++) {
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for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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@ -1156,7 +1159,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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}
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iwl_write_prph(trans, SCD_INTERRUPT_MASK,
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IWL_MASK(0, hw_params(trans).max_txq_num));
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IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
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/* Activate all Tx DMA/FIFO channels */
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iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
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@ -1246,7 +1249,8 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
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}
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/* Unmap DMA from host system and free skb's */
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for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
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for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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txq_id++)
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iwl_tx_queue_unmap(trans, txq_id);
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return 0;
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@ -1685,7 +1689,7 @@ static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
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int ret = 0;
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/* waiting for all the tx frames complete might take a while */
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for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
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for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
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if (cnt == trans_pcie->cmd_queue)
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continue;
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txq = &trans_pcie->txq[cnt];
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@ -1931,7 +1935,9 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
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int pos = 0;
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int cnt;
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int ret;
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const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
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size_t bufsz;
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bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
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if (!trans_pcie->txq) {
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IWL_ERR(trans, "txq not ready\n");
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@ -1941,7 +1947,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
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if (!buf)
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return -ENOMEM;
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for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
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for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
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txq = &trans_pcie->txq[cnt];
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q = &txq->q;
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pos += scnprintf(buf + pos, bufsz - pos,
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