mtd: st_spi_fsm: Supply a busy wait for post-write status
When we write data to the Serial Flash chip we'll wait a predetermined period of time before giving up. During that period of time we poll the status register until completion. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Lee Jones
Brian Norris
Родитель
30ca64f9f9
Коммит
176b437762
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@ -238,8 +238,18 @@
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#define FLASH_CMD_READ4_1_1_4 0x6c
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#define FLASH_CMD_READ4_1_4_4 0xec
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/* Status register */
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#define FLASH_STATUS_BUSY 0x01
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#define FLASH_STATUS_WEL 0x02
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#define FLASH_STATUS_BP0 0x04
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#define FLASH_STATUS_BP1 0x08
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#define FLASH_STATUS_BP2 0x10
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#define FLASH_STATUS_SRWP0 0x80
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#define FLASH_STATUS_TIMEOUT 0xff
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#define FLASH_PAGESIZE 256 /* In Bytes */
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#define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */
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#define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */
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/*
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* Flags to tweak operation of default read/write/erase routines
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@ -519,6 +529,22 @@ static struct stfsm_seq stfsm_seq_read_jedec = {
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SEQ_CFG_STARTSEQ),
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};
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static struct stfsm_seq stfsm_seq_read_status_fifo = {
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.data_size = TRANSFER_SIZE(4),
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.seq_opc[0] = (SEQ_OPC_PADS_1 |
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SEQ_OPC_CYCLES(8) |
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SEQ_OPC_OPCODE(FLASH_CMD_RDSR)),
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.seq = {
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STFSM_INST_CMD1,
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STFSM_INST_DATA_READ,
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STFSM_INST_STOP,
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},
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.seq_cfg = (SEQ_CFG_PADS_1 |
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SEQ_CFG_READNOTWRITE |
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SEQ_CFG_CSDEASSERT |
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SEQ_CFG_STARTSEQ),
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};
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static struct stfsm_seq stfsm_seq_erase_sector = {
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/* 'addr_cfg' configured during initialisation */
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.seq_opc = {
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@ -699,6 +725,53 @@ static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
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return 0;
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}
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static uint8_t stfsm_wait_busy(struct stfsm *fsm)
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{
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struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;
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unsigned long deadline;
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uint32_t status;
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int timeout = 0;
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/* Use RDRS1 */
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seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
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SEQ_OPC_CYCLES(8) |
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SEQ_OPC_OPCODE(FLASH_CMD_RDSR));
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/* Load read_status sequence */
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stfsm_load_seq(fsm, seq);
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/*
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* Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS)
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*/
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deadline = jiffies + FLASH_MAX_BUSY_WAIT;
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while (!timeout) {
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cond_resched();
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if (time_after_eq(jiffies, deadline))
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timeout = 1;
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stfsm_wait_seq(fsm);
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stfsm_read_fifo(fsm, &status, 4);
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if ((status & FLASH_STATUS_BUSY) == 0)
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return 0;
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if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) &&
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((status & S25FL_STATUS_P_ERR) ||
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(status & S25FL_STATUS_E_ERR)))
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return (uint8_t)(status & 0xff);
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if (!timeout)
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/* Restart */
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writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG);
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}
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dev_err(fsm->dev, "timeout on wait_busy\n");
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return FLASH_STATUS_TIMEOUT;
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}
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static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data)
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{
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struct stfsm_seq *seq = &stfsm_seq_wrvcr;
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@ -1020,6 +1093,98 @@ static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
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return 0;
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}
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static int stfsm_write(struct stfsm *fsm, const uint8_t *const buf,
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const uint32_t size, const uint32_t offset)
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{
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struct stfsm_seq *seq = &stfsm_seq_write;
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uint32_t data_pads;
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uint32_t write_mask;
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uint32_t size_ub;
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uint32_t size_lb;
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uint32_t size_mop;
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uint32_t tmp[4];
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uint32_t page_buf[FLASH_PAGESIZE_32];
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uint8_t *t = (uint8_t *)&tmp;
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const uint8_t *p;
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int ret;
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int i;
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dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset);
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/* Enter 32-bit address mode, if required */
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if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)
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stfsm_enter_32bit_addr(fsm, 1);
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/* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */
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data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
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write_mask = (data_pads << 2) - 1;
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/* Handle non-aligned buf */
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if ((uint32_t)buf & 0x3) {
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memcpy(page_buf, buf, size);
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p = (uint8_t *)page_buf;
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} else {
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p = buf;
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}
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/* Handle non-aligned size */
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size_ub = (size + write_mask) & ~write_mask;
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size_lb = size & ~write_mask;
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size_mop = size & write_mask;
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seq->data_size = TRANSFER_SIZE(size_ub);
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seq->addr1 = (offset >> 16) & 0xffff;
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seq->addr2 = offset & 0xffff;
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/* Need to set FIFO to write mode, before writing data to FIFO (see
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* GNBvb79594)
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*/
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writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG);
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/*
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* Before writing data to the FIFO, apply a small delay to allow a
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* potential change of FIFO direction to complete.
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*/
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if (fsm->fifo_dir_delay == 0)
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readl(fsm->base + SPI_FAST_SEQ_CFG);
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else
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udelay(fsm->fifo_dir_delay);
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/* Write data to FIFO, before starting sequence (see GNBvd79593) */
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if (size_lb) {
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stfsm_write_fifo(fsm, (uint32_t *)p, size_lb);
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p += size_lb;
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}
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/* Handle non-aligned size */
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if (size_mop) {
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memset(t, 0xff, write_mask + 1); /* fill with 0xff's */
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for (i = 0; i < size_mop; i++)
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t[i] = *p++;
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stfsm_write_fifo(fsm, tmp, write_mask + 1);
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}
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/* Start sequence */
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stfsm_load_seq(fsm, seq);
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/* Wait for sequence to finish */
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stfsm_wait_seq(fsm);
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/* Wait for completion */
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ret = stfsm_wait_busy(fsm);
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/* Exit 32-bit address mode, if required */
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if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) {
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stfsm_enter_32bit_addr(fsm, 0);
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if (fsm->configuration & CFG_WRITE_EX_32BIT_ADDR_DELAY)
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udelay(1);
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}
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return 0;
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}
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/*
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* Read an address range from the flash chip. The address range
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* may be any size provided it is within the physical boundaries.
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@ -1052,6 +1217,61 @@ static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
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return 0;
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}
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/*
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* Write an address range to the flash chip. Data must be written in
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* FLASH_PAGESIZE chunks. The address range may be any size provided
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* it is within the physical boundaries.
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*/
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static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
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size_t *retlen, const u_char *buf)
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{
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struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
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u32 page_offs;
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u32 bytes;
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uint8_t *b = (uint8_t *)buf;
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int ret = 0;
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dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len);
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*retlen = 0;
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if (!len)
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return 0;
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if (to + len > mtd->size)
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return -EINVAL;
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/* Offset within page */
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page_offs = to % FLASH_PAGESIZE;
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mutex_lock(&fsm->lock);
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while (len) {
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/* Write up to page boundary */
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bytes = min(FLASH_PAGESIZE - page_offs, len);
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ret = stfsm_write(fsm, b, bytes, to);
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if (ret)
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goto out1;
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b += bytes;
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len -= bytes;
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to += bytes;
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/* We are now page-aligned */
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page_offs = 0;
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*retlen += bytes;
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}
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out1:
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mutex_unlock(&fsm->lock);
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return ret;
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}
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static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
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{
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const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
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@ -1308,6 +1528,7 @@ static int stfsm_probe(struct platform_device *pdev)
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fsm->mtd.erasesize = info->sector_size;
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fsm->mtd._read = stfsm_mtd_read;
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fsm->mtd._write = stfsm_mtd_write;
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dev_err(&pdev->dev,
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"Found serial flash device: %s\n"
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