Merge branch 'pci/enumeration'
- Enable PCIe services for host controller drivers that use managed host
bridge alloc (Jean-Philippe Brucker)
- Add quirk to clear PCIe Retrain Link bit to work around Pericom bridge
erratum (Stefan Mätje)
- Add "external-facing" DT property to identify cases where we require
IOMMU protection from untrusted devices (Jean-Philippe Brucker)
- Support fixed bus numbers from bridge Enhanced Allocation capabilities
(Subbaraya Sundeep)
* pci/enumeration:
PCI: Assign bus numbers present in EA capability for bridges
PCI: OF: Support "external-facing" property
dt-bindings: Add "external-facing" PCIe port property
PCI: Rework pcie_retrain_link() wait loop
PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratum
PCI: Factor out pcie_retrain_link() function
PCI: Init PCIe feature bits for managed host bridge alloc
This commit is contained in:
Bjorn Helgaas
Коммит
178901bf6a
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@ -24,3 +24,53 @@ driver implementation may support the following properties:
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unsupported link speed, for instance, trying to do training for
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unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
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for gen2, and '1' for gen1. Any other values are invalid.
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PCI-PCI Bridge properties
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-------------------------
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PCIe root ports and switch ports may be described explicitly in the device
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tree, as children of the host bridge node. Even though those devices are
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discoverable by probing, it might be necessary to describe properties that
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aren't provided by standard PCIe capabilities.
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Required properties:
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- reg:
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Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
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document, it is a five-cell address encoded as (phys.hi phys.mid
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phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
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0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
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The bus number is defined by firmware, through the standard bridge
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configuration mechanism. If this port is a switch port, then firmware
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allocates the bus number and writes it into the Secondary Bus Number
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register of the bridge directly above this port. Otherwise, the bus
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number of a root port is the first number in the bus-range property,
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defaulting to zero.
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If firmware leaves the ARI Forwarding Enable bit set in the bridge
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above this port, then phys.hi contains the 8-bit function number as
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0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
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recommends that firmware only leaves ARI enabled when it knows that the
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OS is ARI-aware.
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Optional properties:
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- external-facing:
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When present, the port is external-facing. All bridges and endpoints
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downstream of this port are external to the machine. The OS can, for
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example, use this information to identify devices that cannot be
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trusted with relaxed DMA protection, as users could easily attach
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malicious devices to this port.
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Example:
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pcie@10000000 {
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compatible = "pci-host-ecam-generic";
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...
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pcie@0008 {
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/* Root port 00:01.0 is external-facing */
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reg = <0x00000800 0 0 0 0>;
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external-facing;
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};
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};
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@ -31,10 +31,16 @@ void pci_release_of_node(struct pci_dev *dev)
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void pci_set_bus_of_node(struct pci_bus *bus)
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{
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if (bus->self == NULL)
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bus->dev.of_node = pcibios_get_phb_of_node(bus);
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else
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bus->dev.of_node = of_node_get(bus->self->dev.of_node);
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struct device_node *node;
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if (bus->self == NULL) {
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node = pcibios_get_phb_of_node(bus);
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} else {
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node = of_node_get(bus->self->dev.of_node);
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if (node && of_property_read_bool(node, "external-facing"))
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bus->self->untrusted = true;
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}
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bus->dev.of_node = node;
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}
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void pci_release_bus_of_node(struct pci_bus *bus)
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@ -196,6 +196,36 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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link->clkpm_capable = (blacklist) ? 0 : capable;
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}
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static bool pcie_retrain_link(struct pcie_link_state *link)
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{
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struct pci_dev *parent = link->pdev;
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unsigned long end_jiffies;
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u16 reg16;
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
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reg16 |= PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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if (parent->clear_retrain_link) {
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/*
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* Due to an erratum in some devices the Retrain Link bit
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* needs to be cleared again manually to allow the link
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* training to succeed.
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*/
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reg16 &= ~PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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}
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/* Wait for link training end. Break out after waiting for timeout */
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end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
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do {
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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msleep(1);
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} while (time_before(jiffies, end_jiffies));
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return !(reg16 & PCI_EXP_LNKSTA_LT);
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}
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/*
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* pcie_aspm_configure_common_clock: check if the 2 ends of a link
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* could use common clock. If they are, configure them to use the
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@ -205,7 +235,6 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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{
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int same_clock = 1;
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u16 reg16, parent_reg, child_reg[8];
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unsigned long start_jiffies;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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/*
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@ -263,21 +292,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Retrain link */
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reg16 |= PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end. Break out after waiting for timeout */
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start_jiffies = jiffies;
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for (;;) {
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
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break;
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msleep(1);
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}
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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if (pcie_retrain_link(link))
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return;
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/* Training failed. Restore common clock configurations */
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@ -586,16 +586,9 @@ static void pci_release_host_bridge_dev(struct device *dev)
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kfree(to_pci_host_bridge(dev));
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}
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struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
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static void pci_init_host_bridge(struct pci_host_bridge *bridge)
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{
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struct pci_host_bridge *bridge;
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bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
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if (!bridge)
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return NULL;
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INIT_LIST_HEAD(&bridge->windows);
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bridge->dev.release = pci_release_host_bridge_dev;
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/*
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* We assume we can manage these PCIe features. Some systems may
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@ -608,6 +601,18 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
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bridge->native_shpc_hotplug = 1;
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bridge->native_pme = 1;
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bridge->native_ltr = 1;
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}
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struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
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{
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struct pci_host_bridge *bridge;
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bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
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if (!bridge)
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return NULL;
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pci_init_host_bridge(bridge);
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bridge->dev.release = pci_release_host_bridge_dev;
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return bridge;
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}
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@ -622,7 +627,7 @@ struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
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if (!bridge)
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return NULL;
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INIT_LIST_HEAD(&bridge->windows);
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pci_init_host_bridge(bridge);
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bridge->dev.release = devm_pci_release_host_bridge_dev;
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return bridge;
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@ -1081,6 +1086,36 @@ static void pci_enable_crs(struct pci_dev *pdev)
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static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
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unsigned int available_buses);
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/**
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* pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
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* numbers from EA capability.
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* @dev: Bridge
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* @sec: updated with secondary bus number from EA
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* @sub: updated with subordinate bus number from EA
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*
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* If @dev is a bridge with EA capability, update @sec and @sub with
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* fixed bus numbers from the capability and return true. Otherwise,
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* return false.
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*/
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static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
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{
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int ea, offset;
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u32 dw;
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if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
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return false;
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/* find PCI EA capability in list */
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ea = pci_find_capability(dev, PCI_CAP_ID_EA);
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if (!ea)
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return false;
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offset = ea + PCI_EA_FIRST_ENT;
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pci_read_config_dword(dev, offset, &dw);
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*sec = dw & PCI_EA_SEC_BUS_MASK;
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*sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
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return true;
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}
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/*
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* pci_scan_bridge_extend() - Scan buses behind a bridge
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@ -1115,6 +1150,9 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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u16 bctl;
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u8 primary, secondary, subordinate;
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int broken = 0;
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bool fixed_buses;
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u8 fixed_sec, fixed_sub;
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int next_busnr;
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/*
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* Make sure the bridge is powered on to be able to access config
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@ -1214,17 +1252,24 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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/* Clear errors */
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pci_write_config_word(dev, PCI_STATUS, 0xffff);
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/* Read bus numbers from EA Capability (if present) */
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fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
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if (fixed_buses)
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next_busnr = fixed_sec;
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else
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next_busnr = max + 1;
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/*
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* Prevent assigning a bus number that already exists.
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* This can happen when a bridge is hot-plugged, so in this
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* case we only re-scan this bus.
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*/
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child = pci_find_bus(pci_domain_nr(bus), max+1);
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child = pci_find_bus(pci_domain_nr(bus), next_busnr);
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if (!child) {
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child = pci_add_new_bus(bus, dev, max+1);
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child = pci_add_new_bus(bus, dev, next_busnr);
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if (!child)
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goto out;
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pci_bus_insert_busn_res(child, max+1,
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pci_bus_insert_busn_res(child, next_busnr,
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bus->busn_res.end);
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}
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max++;
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@ -1285,7 +1330,13 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
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max += i;
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}
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/* Set subordinate bus number to its real value */
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/*
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* Set subordinate bus number to its real value.
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* If fixed subordinate bus number exists from EA
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* capability then use it.
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*/
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if (fixed_buses)
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max = fixed_sub;
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pci_bus_update_busn_res_end(child, max);
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
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}
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@ -2245,6 +2245,23 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
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/*
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* Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
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* Link bit cleared after starting the link retrain process to allow this
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* process to finish.
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*
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* Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
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* Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
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*/
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static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
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{
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dev->clear_retrain_link = 1;
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pci_info(dev, "Enable PCIe Retrain Link quirk\n");
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}
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DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
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DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
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DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
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static void fixup_rev1_53c810(struct pci_dev *dev)
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{
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u32 class = dev->class;
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@ -348,6 +348,8 @@ struct pci_dev {
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unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
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controlled exclusively by
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user sysfs */
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unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
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bit manually */
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unsigned int d3_delay; /* D3->D0 transition time in ms */
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unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
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@ -372,6 +372,12 @@
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#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
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#define PCI_EA_ES 0x00000007 /* Entry Size */
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#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
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/* EA fixed Secondary and Subordinate bus numbers for Bridge */
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#define PCI_EA_SEC_BUS_MASK 0xff
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#define PCI_EA_SUB_BUS_MASK 0xff00
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#define PCI_EA_SUB_BUS_SHIFT 8
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/* 0-5 map to BARs 0-5 respectively */
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#define PCI_EA_BEI_BAR0 0
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#define PCI_EA_BEI_BAR5 5
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