drm/i915/hdmi: Change the write_infoframe vfunc to take a buffer and a type
First step in the move to the shared infoframe infrastructure, let's move the different infoframe helpers and the write_infoframe() vfunc to a type (enum hdmi_infoframe_type) and a buffer + len instead of using our struct dip_infoframe. v2: constify the infoframe pointer and don't mix signs (Ville Syrjälä) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau
Daniel Vetter
Родитель
03a7a189c2
Коммит
178f736ab9
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@ -26,6 +26,7 @@
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#define __INTEL_DRV_H__
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#include <linux/i2c.h>
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#include <linux/hdmi.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
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@ -464,7 +465,8 @@ struct intel_hdmi {
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enum hdmi_force_audio force_audio;
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bool rgb_quant_range_selectable;
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void (*write_infoframe)(struct drm_encoder *encoder,
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struct dip_infoframe *frame);
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len);
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void (*set_infoframes)(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode);
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};
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@ -29,6 +29,7 @@
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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@ -81,74 +82,75 @@ void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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frame->checksum = 0x100 - sum;
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}
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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
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static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_SELECT_AVI;
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case DIP_TYPE_SPD:
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_SELECT_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
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static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI;
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case DIP_TYPE_SPD:
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
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static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI_HSW;
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case DIP_TYPE_SPD:
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD_HSW;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
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static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
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enum transcoder cpu_transcoder)
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
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case DIP_TYPE_SPD:
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case HDMI_INFOFRAME_TYPE_SPD:
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return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static void g4x_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val = I915_READ(VIDEO_DIP_CTL);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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int i;
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(frame);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(VIDEO_DIP_CTL, val);
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@ -162,7 +164,7 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
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I915_WRITE(VIDEO_DIP_DATA, 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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@ -171,22 +173,22 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
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}
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static void ibx_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(frame);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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@ -200,7 +202,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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@ -209,25 +211,25 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
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}
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static void cpt_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val |= g4x_infoframe_index(type);
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/* The DIP control register spec says that we need to update the AVI
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* infoframe without clearing its enable bit */
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if (frame->type != DIP_TYPE_AVI)
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val &= ~g4x_infoframe_enable(frame);
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if (type != HDMI_INFOFRAME_TYPE_AVI)
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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@ -241,7 +243,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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@ -250,22 +252,22 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(frame);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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@ -279,7 +281,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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@ -288,21 +290,24 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
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}
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static void hsw_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
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u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
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unsigned int i, len = DIP_HEADER_SIZE + frame->len;
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u32 data_reg;
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int i;
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u32 val = I915_READ(ctl_reg);
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data_reg = hsw_infoframe_data_reg(type,
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intel_crtc->config.cpu_transcoder);
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if (data_reg == 0)
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return;
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val &= ~hsw_infoframe_enable(frame);
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val &= ~hsw_infoframe_enable(type);
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I915_WRITE(ctl_reg, val);
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mmiowb();
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@ -315,7 +320,7 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
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I915_WRITE(data_reg + i, 0);
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mmiowb();
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val |= hsw_infoframe_enable(frame);
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val |= hsw_infoframe_enable(type);
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I915_WRITE(ctl_reg, val);
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POSTING_READ(ctl_reg);
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}
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@ -326,7 +331,8 @@ static void intel_set_infoframe(struct drm_encoder *encoder,
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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intel_dip_infoframe_csum(frame);
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intel_hdmi->write_infoframe(encoder, frame);
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intel_hdmi->write_infoframe(encoder, frame->type, (uint8_t *)frame,
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DIP_HEADER_SIZE + frame->len);
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}
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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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