Merge 4.10-rc7 into char-misc-next
We want the hv and other fixes in here as well to handle merge and testing issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
Коммит
17fa87fe5a
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@ -15,6 +15,9 @@ Properties:
|
|||
Second cell specifies the irq distribution mode to cores
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||||
0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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|
||||
The second cell in interrupts property is deprecated and may be ignored by
|
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the kernel.
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||||
|
||||
intc accessed via the special ARC AUX register interface, hence "reg" property
|
||||
is not specified.
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ Required properties:
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|||
- compatible: "sigma,smp8758-nand"
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- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
|
||||
- dmas: reference to the DMA channel used by the controller
|
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- dma-names: "nfc_sbox"
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||||
- dma-names: "rxtx"
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- clocks: reference to the system clock
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- #address-cells: <1>
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- #size-cells: <0>
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|
|
@ -17,9 +17,9 @@ Example:
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nandc: nand-controller@2c000 {
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compatible = "sigma,smp8758-nand";
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reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;
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reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
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dmas = <&dma0 3>;
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dma-names = "nfc_sbox";
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dma-names = "rxtx";
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clocks = <&clkgen SYS_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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|
|
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|
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@ -7,7 +7,7 @@ have dual GMAC each represented by a child node..
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* Ethernet controller node
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Required properties:
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- compatible: Should be "mediatek,mt7623-eth"
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- compatible: Should be "mediatek,mt2701-eth"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the three frame engines interrupts in numeric
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order. These are fe_int0, fe_int1 and fe_int2.
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|
|
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|
|
@ -19,8 +19,9 @@ Optional Properties:
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specifications. If neither of these are specified, the default is to
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assume clause 22.
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|
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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If the PHY reports an incorrect ID (or none at all) then the
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"compatible" list may contain an entry with the correct PHY ID in the
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form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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|
|
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@ -3,9 +3,11 @@
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
|
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
|
||||
for applicable values. Required only if interface type is
|
||||
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
|
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
|
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for applicable values
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|
|
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|
|
@ -1,17 +1,23 @@
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|||
Renesas MSIOF spi controller
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|
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Required properties:
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- compatible : "renesas,msiof-<soctype>" for SoCs,
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"renesas,sh-msiof" for SuperH, or
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"renesas,sh-mobile-msiof" for SH Mobile series.
|
||||
Examples with soctypes are:
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"renesas,msiof-r8a7790" (R-Car H2)
|
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- compatible : "renesas,msiof-r8a7790" (R-Car H2)
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"renesas,msiof-r8a7791" (R-Car M2-W)
|
||||
"renesas,msiof-r8a7792" (R-Car V2H)
|
||||
"renesas,msiof-r8a7793" (R-Car M2-N)
|
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"renesas,msiof-r8a7794" (R-Car E2)
|
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"renesas,msiof-r8a7796" (R-Car M3-W)
|
||||
"renesas,msiof-sh73a0" (SH-Mobile AG5)
|
||||
"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
|
||||
"renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
|
||||
"renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
|
||||
"renesas,sh-msiof" (deprecated)
|
||||
|
||||
When compatible with the generic version, nodes
|
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must list the SoC-specific version corresponding
|
||||
to the platform first followed by the generic
|
||||
version.
|
||||
|
||||
- reg : A list of offsets and lengths of the register sets for
|
||||
the device.
|
||||
If only one register set is present, it is to be used
|
||||
|
|
@ -61,7 +67,8 @@ Documentation/devicetree/bindings/pinctrl/renesas,*.
|
|||
Example:
|
||||
|
||||
msiof0: spi@e6e20000 {
|
||||
compatible = "renesas,msiof-r8a7791";
|
||||
compatible = "renesas,msiof-r8a7791",
|
||||
"renesas,rcar-gen2-msiof";
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||||
reg = <0 0xe6e20000 0 0x0064>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
||||
|
|
|
|||
|
|
@ -212,10 +212,11 @@ asynchronous manner and the value may not be very precise. To see a precise
|
|||
snapshot of a moment, you can see /proc/<pid>/smaps file and scan page table.
|
||||
It's slow but very precise.
|
||||
|
||||
Table 1-2: Contents of the status files (as of 4.1)
|
||||
Table 1-2: Contents of the status files (as of 4.8)
|
||||
..............................................................................
|
||||
Field Content
|
||||
Name filename of the executable
|
||||
Umask file mode creation mask
|
||||
State state (R is running, S is sleeping, D is sleeping
|
||||
in an uninterruptible wait, Z is zombie,
|
||||
T is traced or stopped)
|
||||
|
|
@ -226,7 +227,6 @@ Table 1-2: Contents of the status files (as of 4.1)
|
|||
TracerPid PID of process tracing this process (0 if not)
|
||||
Uid Real, effective, saved set, and file system UIDs
|
||||
Gid Real, effective, saved set, and file system GIDs
|
||||
Umask file mode creation mask
|
||||
FDSize number of file descriptor slots currently allocated
|
||||
Groups supplementary group list
|
||||
NStgid descendant namespace thread group ID hierarchy
|
||||
|
|
@ -236,6 +236,7 @@ Table 1-2: Contents of the status files (as of 4.1)
|
|||
VmPeak peak virtual memory size
|
||||
VmSize total program size
|
||||
VmLck locked memory size
|
||||
VmPin pinned memory size
|
||||
VmHWM peak resident set size ("high water mark")
|
||||
VmRSS size of memory portions. It contains the three
|
||||
following parts (VmRSS = RssAnon + RssFile + RssShmem)
|
||||
|
|
|
|||
|
|
@ -35,9 +35,7 @@ only one way to cause the system to go into the Suspend-To-RAM state (write
|
|||
The default suspend mode (ie. the one to be used without writing anything into
|
||||
/sys/power/mem_sleep) is either "deep" (if Suspend-To-RAM is supported) or
|
||||
"s2idle", but it can be overridden by the value of the "mem_sleep_default"
|
||||
parameter in the kernel command line. On some ACPI-based systems, depending on
|
||||
the information in the FADT, the default may be "s2idle" even if Suspend-To-RAM
|
||||
is supported.
|
||||
parameter in the kernel command line.
|
||||
|
||||
The properties of all of the sleep states are described below.
|
||||
|
||||
|
|
|
|||
37
MAINTAINERS
37
MAINTAINERS
|
|
@ -976,6 +976,7 @@ M: Russell King <linux@armlinux.org.uk>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.armlinux.org.uk/
|
||||
S: Maintained
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git
|
||||
F: arch/arm/
|
||||
|
||||
ARM SUB-ARCHITECTURES
|
||||
|
|
@ -1153,6 +1154,7 @@ ARM/CLKDEV SUPPORT
|
|||
M: Russell King <linux@armlinux.org.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev
|
||||
F: arch/arm/include/asm/clkdev.h
|
||||
F: drivers/clk/clkdev.c
|
||||
|
||||
|
|
@ -1688,6 +1690,7 @@ M: Krzysztof Kozlowski <krzk@kernel.org>
|
|||
R: Javier Martinez Canillas <javier@osg.samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/s3c*
|
||||
F: arch/arm/boot/dts/s5p*
|
||||
|
|
@ -3564,7 +3567,7 @@ F: drivers/infiniband/hw/cxgb3/
|
|||
F: include/uapi/rdma/cxgb3-abi.h
|
||||
|
||||
CXGB4 ETHERNET DRIVER (CXGB4)
|
||||
M: Hariprasad S <hariprasad@chelsio.com>
|
||||
M: Ganesh Goudar <ganeshgr@chelsio.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.chelsio.com
|
||||
S: Supported
|
||||
|
|
@ -4097,12 +4100,18 @@ F: drivers/gpu/drm/bridge/
|
|||
|
||||
DRM DRIVER FOR BOCHS VIRTUAL GPU
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
S: Odd Fixes
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
T: git git://git.kraxel.org/linux drm-qemu
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/bochs/
|
||||
|
||||
DRM DRIVER FOR QEMU'S CIRRUS DEVICE
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
T: git git://git.kraxel.org/linux drm-qemu
|
||||
S: Obsolete
|
||||
W: https://www.kraxel.org/blog/2014/10/qemu-using-cirrus-considered-harmful/
|
||||
F: drivers/gpu/drm/cirrus/
|
||||
|
||||
RADEON and AMDGPU DRM DRIVERS
|
||||
|
|
@ -4144,7 +4153,7 @@ F: Documentation/gpu/i915.rst
|
|||
INTEL GVT-g DRIVERS (Intel GPU Virtualization)
|
||||
M: Zhenyu Wang <zhenyuw@linux.intel.com>
|
||||
M: Zhi Wang <zhi.a.wang@intel.com>
|
||||
L: igvt-g-dev@lists.01.org
|
||||
L: intel-gvt-dev@lists.freedesktop.org
|
||||
L: intel-gfx@lists.freedesktop.org
|
||||
W: https://01.org/igvt-g
|
||||
T: git https://github.com/01org/gvt-linux.git
|
||||
|
|
@ -4295,7 +4304,10 @@ F: Documentation/devicetree/bindings/display/renesas,du.txt
|
|||
|
||||
DRM DRIVER FOR QXL VIRTUAL GPU
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
S: Odd Fixes
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
T: git git://git.kraxel.org/linux drm-qemu
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/qxl/
|
||||
F: include/uapi/drm/qxl_drm.h
|
||||
|
||||
|
|
@ -7698,8 +7710,10 @@ F: drivers/net/dsa/mv88e6xxx/
|
|||
F: Documentation/devicetree/bindings/net/dsa/marvell.txt
|
||||
|
||||
MARVELL ARMADA DRM SUPPORT
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Maintained
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
|
||||
F: drivers/gpu/drm/armada/
|
||||
F: include/uapi/drm/armada_drm.h
|
||||
F: Documentation/devicetree/bindings/display/armada/
|
||||
|
|
@ -8904,8 +8918,10 @@ S: Supported
|
|||
F: drivers/nfc/nxp-nci
|
||||
|
||||
NXP TDA998X DRM DRIVER
|
||||
M: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
S: Supported
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-devel
|
||||
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-fixes
|
||||
F: drivers/gpu/drm/i2c/tda998x_drv.c
|
||||
F: include/drm/i2c/tda998x.h
|
||||
|
||||
|
|
@ -10180,7 +10196,6 @@ F: drivers/media/tuners/qt1010*
|
|||
QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
|
||||
M: QCA ath9k Development <ath9k-devel@qca.qualcomm.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
L: ath9k-devel@lists.ath9k.org
|
||||
W: http://wireless.kernel.org/en/users/Drivers/ath9k
|
||||
S: Supported
|
||||
F: drivers/net/wireless/ath/ath9k/
|
||||
|
|
@ -13051,7 +13066,7 @@ F: drivers/input/serio/userio.c
|
|||
F: include/uapi/linux/userio.h
|
||||
|
||||
VIRTIO CONSOLE DRIVER
|
||||
M: Amit Shah <amit.shah@redhat.com>
|
||||
M: Amit Shah <amit@kernel.org>
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
S: Maintained
|
||||
F: drivers/char/virtio_console.c
|
||||
|
|
@ -13086,6 +13101,7 @@ M: David Airlie <airlied@linux.ie>
|
|||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: virtualization@lists.linux-foundation.org
|
||||
T: git git://git.kraxel.org/linux drm-qemu
|
||||
S: Maintained
|
||||
F: drivers/gpu/drm/virtio/
|
||||
F: include/uapi/linux/virtio_gpu.h
|
||||
|
|
@ -13437,6 +13453,7 @@ F: arch/x86/
|
|||
|
||||
X86 PLATFORM DRIVERS
|
||||
M: Darren Hart <dvhart@infradead.org>
|
||||
M: Andy Shevchenko <andy@infradead.org>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
T: git git://git.infradead.org/users/dvhart/linux-platform-drivers-x86.git
|
||||
S: Maintained
|
||||
|
|
@ -13608,6 +13625,7 @@ F: drivers/net/hamradio/z8530.h
|
|||
|
||||
ZBUD COMPRESSED PAGE ALLOCATOR
|
||||
M: Seth Jennings <sjenning@redhat.com>
|
||||
M: Dan Streetman <ddstreet@ieee.org>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/zbud.c
|
||||
|
|
@ -13663,6 +13681,7 @@ F: Documentation/vm/zsmalloc.txt
|
|||
|
||||
ZSWAP COMPRESSED SWAP CACHING
|
||||
M: Seth Jennings <sjenning@redhat.com>
|
||||
M: Dan Streetman <ddstreet@ieee.org>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/zswap.c
|
||||
|
|
|
|||
6
Makefile
6
Makefile
|
|
@ -1,8 +1,8 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 10
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Roaring Lionus
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Fearless Coyote
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
|
@ -797,7 +797,7 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types)
|
|||
KBUILD_ARFLAGS := $(call ar-option,D)
|
||||
|
||||
# check for 'asm goto'
|
||||
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC)), y)
|
||||
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)
|
||||
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
|
||||
KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ config ARC
|
|||
select HAVE_KPROBES
|
||||
select HAVE_KRETPROBES
|
||||
select HAVE_MEMBLOCK
|
||||
select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select HAVE_OPROFILE
|
||||
select HAVE_PERF_EVENTS
|
||||
select HANDLE_DOMAIN_IRQ
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ extern unsigned long perip_base, perip_end;
|
|||
#define ARC_REG_IC_PTAG_HI 0x1F
|
||||
|
||||
/* Bit val in IC_CTRL */
|
||||
#define IC_CTRL_CACHE_DISABLE 0x1
|
||||
#define IC_CTRL_DIS 0x1
|
||||
|
||||
/* Data cache related Auxiliary registers */
|
||||
#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
|
||||
|
|
@ -80,8 +80,9 @@ extern unsigned long perip_base, perip_end;
|
|||
#define ARC_REG_DC_PTAG_HI 0x5F
|
||||
|
||||
/* Bit val in DC_CTRL */
|
||||
#define DC_CTRL_INV_MODE_FLUSH 0x40
|
||||
#define DC_CTRL_FLUSH_STATUS 0x100
|
||||
#define DC_CTRL_DIS 0x001
|
||||
#define DC_CTRL_INV_MODE_FLUSH 0x040
|
||||
#define DC_CTRL_FLUSH_STATUS 0x100
|
||||
|
||||
/*System-level cache (L2 cache) related Auxiliary registers */
|
||||
#define ARC_REG_SLC_CFG 0x901
|
||||
|
|
@ -92,8 +93,8 @@ extern unsigned long perip_base, perip_end;
|
|||
#define ARC_REG_SLC_RGN_END 0x916
|
||||
|
||||
/* Bit val in SLC_CONTROL */
|
||||
#define SLC_CTRL_DIS 0x001
|
||||
#define SLC_CTRL_IM 0x040
|
||||
#define SLC_CTRL_DISABLE 0x001
|
||||
#define SLC_CTRL_BUSY 0x100
|
||||
#define SLC_CTRL_RGN_OP_INV 0x200
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@ static inline void __delay(unsigned long loops)
|
|||
" lp 1f \n"
|
||||
" nop \n"
|
||||
"1: \n"
|
||||
: : "r"(loops));
|
||||
:
|
||||
: "r"(loops)
|
||||
: "lp_count");
|
||||
}
|
||||
|
||||
extern void __bad_udelay(void);
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
;
|
||||
; Now manually save: r12, sp, fp, gp, r25
|
||||
|
||||
PUSH r30
|
||||
PUSH r12
|
||||
|
||||
; Saving pt_regs->sp correctly requires some extra work due to the way
|
||||
|
|
@ -72,6 +73,7 @@
|
|||
POPAX AUX_USER_SP
|
||||
1:
|
||||
POP r12
|
||||
POP r30
|
||||
|
||||
.endm
|
||||
|
||||
|
|
|
|||
|
|
@ -14,13 +14,13 @@
|
|||
|
||||
#include <asm-generic/module.h>
|
||||
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
struct mod_arch_specific {
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
void *unw_info;
|
||||
int unw_sec_idx;
|
||||
#endif
|
||||
const char *secstr;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define MODULE_PROC_FAMILY "ARC700"
|
||||
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ struct pt_regs {
|
|||
unsigned long fp;
|
||||
unsigned long sp; /* user/kernel sp depending on where we came from */
|
||||
|
||||
unsigned long r12;
|
||||
unsigned long r12, r30;
|
||||
|
||||
/*------- Below list auto saved by h/w -----------*/
|
||||
unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ extern int root_mountflags, end_mem;
|
|||
|
||||
void setup_processor(void);
|
||||
void __init setup_arch_memory(void);
|
||||
long __init arc_get_mem_sz(void);
|
||||
|
||||
/* Helpers used in arc_*_mumbojumbo routines */
|
||||
#define IS_AVAIL1(v, s) ((v) ? s : "")
|
||||
|
|
|
|||
|
|
@ -71,14 +71,14 @@ ENTRY(stext)
|
|||
GET_CPU_ID r5
|
||||
cmp r5, 0
|
||||
mov.nz r0, r5
|
||||
#ifdef CONFIG_ARC_SMP_HALT_ON_RESET
|
||||
; Non-Master can proceed as system would be booted sufficiently
|
||||
jnz first_lines_of_secondary
|
||||
#else
|
||||
bz .Lmaster_proceed
|
||||
|
||||
; Non-Masters wait for Master to boot enough and bring them up
|
||||
jnz arc_platform_smp_wait_to_boot
|
||||
#endif
|
||||
; Master falls thru
|
||||
; when they resume, tail-call to entry point
|
||||
mov blink, @first_lines_of_secondary
|
||||
j arc_platform_smp_wait_to_boot
|
||||
|
||||
.Lmaster_proceed:
|
||||
#endif
|
||||
|
||||
; Clear BSS before updating any globals
|
||||
|
|
|
|||
|
|
@ -77,20 +77,20 @@ void arc_init_IRQ(void)
|
|||
|
||||
static void arcv2_irq_mask(struct irq_data *data)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_ENABLE, 0);
|
||||
}
|
||||
|
||||
static void arcv2_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_ENABLE, 1);
|
||||
}
|
||||
|
||||
void arcv2_irq_enable(struct irq_data *data)
|
||||
{
|
||||
/* set default priority */
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ static void arc_irq_mask(struct irq_data *data)
|
|||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb &= ~(1 << data->irq);
|
||||
ienb &= ~(1 << data->hwirq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
|
|
@ -66,7 +66,7 @@ static void arc_irq_unmask(struct irq_data *data)
|
|||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb |= (1 << data->irq);
|
||||
ienb |= (1 << data->hwirq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
#include <linux/smp.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <soc/arc/mcip.h>
|
||||
#include <asm/irqflags-arcv2.h>
|
||||
|
|
@ -92,11 +93,10 @@ static void mcip_probe_n_setup(void)
|
|||
READ_BCR(ARC_REG_MCIP_BCR, mp);
|
||||
|
||||
sprintf(smp_cpuinfo_buf,
|
||||
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
|
||||
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
|
||||
mp.ver, mp.num_cores,
|
||||
IS_AVAIL1(mp.ipi, "IPI "),
|
||||
IS_AVAIL1(mp.idu, "IDU "),
|
||||
IS_AVAIL1(mp.llm, "LLM "),
|
||||
IS_AVAIL1(mp.dbg, "DEBUG "),
|
||||
IS_AVAIL1(mp.gfrc, "GFRC"));
|
||||
|
||||
|
|
@ -174,7 +174,6 @@ static void idu_irq_unmask(struct irq_data *data)
|
|||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int
|
||||
idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
|
||||
bool force)
|
||||
|
|
@ -204,12 +203,27 @@ idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
|
|||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void idu_irq_enable(struct irq_data *data)
|
||||
{
|
||||
/*
|
||||
* By default send all common interrupts to all available online CPUs.
|
||||
* The affinity of common interrupts in IDU must be set manually since
|
||||
* in some cases the kernel will not call irq_set_affinity() by itself:
|
||||
* 1. When the kernel is not configured with support of SMP.
|
||||
* 2. When the kernel is configured with support of SMP but upper
|
||||
* interrupt controllers does not support setting of the affinity
|
||||
* and cannot propagate it to IDU.
|
||||
*/
|
||||
idu_irq_set_affinity(data, cpu_online_mask, false);
|
||||
idu_irq_unmask(data);
|
||||
}
|
||||
|
||||
static struct irq_chip idu_irq_chip = {
|
||||
.name = "MCIP IDU Intc",
|
||||
.irq_mask = idu_irq_mask,
|
||||
.irq_unmask = idu_irq_unmask,
|
||||
.irq_enable = idu_irq_enable,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = idu_irq_set_affinity,
|
||||
#endif
|
||||
|
|
@ -221,10 +235,13 @@ static irq_hw_number_t idu_first_hwirq;
|
|||
static void idu_cascade_isr(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *core_chip = irq_desc_get_chip(desc);
|
||||
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
|
||||
irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
|
||||
|
||||
chained_irq_enter(core_chip, desc);
|
||||
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
|
||||
chained_irq_exit(core_chip, desc);
|
||||
}
|
||||
|
||||
static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
|
||||
|
|
@ -239,36 +256,14 @@ static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
|
|||
const u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq, unsigned int *out_type)
|
||||
{
|
||||
irq_hw_number_t hwirq = *out_hwirq = intspec[0];
|
||||
int distri = intspec[1];
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* Ignore value of interrupt distribution mode for common interrupts in
|
||||
* IDU which resides in intspec[1] since setting an affinity using value
|
||||
* from Device Tree is deprecated in ARC.
|
||||
*/
|
||||
*out_hwirq = intspec[0];
|
||||
*out_type = IRQ_TYPE_NONE;
|
||||
|
||||
/* XXX: validate distribution scheme again online cpu mask */
|
||||
if (distri == 0) {
|
||||
/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
|
||||
idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
} else {
|
||||
/*
|
||||
* DEST based distribution for Level Triggered intr can only
|
||||
* have 1 CPU, so generalize it to always contain 1 cpu
|
||||
*/
|
||||
int cpu = ffs(distri);
|
||||
|
||||
if (cpu != fls(distri))
|
||||
pr_warn("IDU irq %lx distri mode set to cpu %x\n",
|
||||
hwirq, cpu);
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
idu_set_dest(hwirq, cpu);
|
||||
idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,8 +32,8 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
|
|||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
mod->arch.unw_sec_idx = 0;
|
||||
mod->arch.unw_info = NULL;
|
||||
mod->arch.secstr = secstr;
|
||||
#endif
|
||||
mod->arch.secstr = secstr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -113,8 +113,10 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
|
|||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0)
|
||||
module->arch.unw_sec_idx = tgtsec;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -90,22 +90,37 @@ void __init smp_cpus_done(unsigned int max_cpus)
|
|||
*/
|
||||
static volatile int wake_flag;
|
||||
|
||||
#ifdef CONFIG_ISA_ARCOMPACT
|
||||
|
||||
#define __boot_read(f) f
|
||||
#define __boot_write(f, v) f = v
|
||||
|
||||
#else
|
||||
|
||||
#define __boot_read(f) arc_read_uncached_32(&f)
|
||||
#define __boot_write(f, v) arc_write_uncached_32(&f, v)
|
||||
|
||||
#endif
|
||||
|
||||
static void arc_default_smp_cpu_kick(int cpu, unsigned long pc)
|
||||
{
|
||||
BUG_ON(cpu == 0);
|
||||
wake_flag = cpu;
|
||||
|
||||
__boot_write(wake_flag, cpu);
|
||||
}
|
||||
|
||||
void arc_platform_smp_wait_to_boot(int cpu)
|
||||
{
|
||||
while (wake_flag != cpu)
|
||||
/* for halt-on-reset, we've waited already */
|
||||
if (IS_ENABLED(CONFIG_ARC_SMP_HALT_ON_RESET))
|
||||
return;
|
||||
|
||||
while (__boot_read(wake_flag) != cpu)
|
||||
;
|
||||
|
||||
wake_flag = 0;
|
||||
__asm__ __volatile__("j @first_lines_of_secondary \n");
|
||||
__boot_write(wake_flag, 0);
|
||||
}
|
||||
|
||||
|
||||
const char *arc_platform_smp_cpuinfo(void)
|
||||
{
|
||||
return plat_smp_ops.info ? : "";
|
||||
|
|
|
|||
|
|
@ -241,8 +241,9 @@ int misaligned_fixup(unsigned long address, struct pt_regs *regs,
|
|||
if (state.fault)
|
||||
goto fault;
|
||||
|
||||
/* clear any remanants of delay slot */
|
||||
if (delay_mode(regs)) {
|
||||
regs->ret = regs->bta;
|
||||
regs->ret = regs->bta ~1U;
|
||||
regs->status32 &= ~STATUS_DE_MASK;
|
||||
} else {
|
||||
regs->ret += state.instr_len;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
static int l2_line_sz;
|
||||
static int ioc_exists;
|
||||
int slc_enable = 1, ioc_enable = 0;
|
||||
int slc_enable = 1, ioc_enable = 1;
|
||||
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
|
||||
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
|
||||
|
||||
|
|
@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
|
|||
|
||||
/*
|
||||
* For ARC700 MMUv3 I-cache and D-cache flushes
|
||||
* Also reused for HS38 aliasing I-cache configuration
|
||||
* - ARC700 programming model requires paddr and vaddr be passed in seperate
|
||||
* AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
|
||||
* caches actually alias or not.
|
||||
* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
|
||||
* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
|
||||
*/
|
||||
static inline
|
||||
void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
|
||||
|
|
@ -458,6 +462,21 @@ static inline void __dc_entire_op(const int op)
|
|||
__after_dc_op(op);
|
||||
}
|
||||
|
||||
static inline void __dc_disable(void)
|
||||
{
|
||||
const int r = ARC_REG_DC_CTRL;
|
||||
|
||||
__dc_entire_op(OP_FLUSH_N_INV);
|
||||
write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
|
||||
}
|
||||
|
||||
static void __dc_enable(void)
|
||||
{
|
||||
const int r = ARC_REG_DC_CTRL;
|
||||
|
||||
write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
|
||||
}
|
||||
|
||||
/* For kernel mappings cache operation: index is same as paddr */
|
||||
#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
|
||||
|
||||
|
|
@ -483,6 +502,8 @@ static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
|
|||
#else
|
||||
|
||||
#define __dc_entire_op(op)
|
||||
#define __dc_disable()
|
||||
#define __dc_enable()
|
||||
#define __dc_line_op(paddr, vaddr, sz, op)
|
||||
#define __dc_line_op_k(paddr, sz, op)
|
||||
|
||||
|
|
@ -597,6 +618,40 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
|
|||
#endif
|
||||
}
|
||||
|
||||
noinline static void slc_entire_op(const int op)
|
||||
{
|
||||
unsigned int ctrl, r = ARC_REG_SLC_CTRL;
|
||||
|
||||
ctrl = read_aux_reg(r);
|
||||
|
||||
if (!(op & OP_FLUSH)) /* i.e. OP_INV */
|
||||
ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
|
||||
else
|
||||
ctrl |= SLC_CTRL_IM;
|
||||
|
||||
write_aux_reg(r, ctrl);
|
||||
|
||||
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
|
||||
|
||||
/* Important to wait for flush to complete */
|
||||
while (read_aux_reg(r) & SLC_CTRL_BUSY);
|
||||
}
|
||||
|
||||
static inline void arc_slc_disable(void)
|
||||
{
|
||||
const int r = ARC_REG_SLC_CTRL;
|
||||
|
||||
slc_entire_op(OP_FLUSH_N_INV);
|
||||
write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
|
||||
}
|
||||
|
||||
static inline void arc_slc_enable(void)
|
||||
{
|
||||
const int r = ARC_REG_SLC_CTRL;
|
||||
|
||||
write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
|
||||
}
|
||||
|
||||
/***********************************************************
|
||||
* Exported APIs
|
||||
*/
|
||||
|
|
@ -923,21 +978,54 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void arc_cache_init(void)
|
||||
/*
|
||||
* IO-Coherency (IOC) setup rules:
|
||||
*
|
||||
* 1. Needs to be at system level, so only once by Master core
|
||||
* Non-Masters need not be accessing caches at that time
|
||||
* - They are either HALT_ON_RESET and kick started much later or
|
||||
* - if run on reset, need to ensure that arc_platform_smp_wait_to_boot()
|
||||
* doesn't perturb caches or coherency unit
|
||||
*
|
||||
* 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
|
||||
* otherwise any straggler data might behave strangely post IOC enabling
|
||||
*
|
||||
* 3. All Caches need to be disabled when setting up IOC to elide any in-flight
|
||||
* Coherency transactions
|
||||
*/
|
||||
noinline void __init arc_ioc_setup(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
char str[256];
|
||||
unsigned int ap_sz;
|
||||
|
||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||
/* Flush + invalidate + disable L1 dcache */
|
||||
__dc_disable();
|
||||
|
||||
/* Flush + invalidate SLC */
|
||||
if (read_aux_reg(ARC_REG_SLC_BCR))
|
||||
slc_entire_op(OP_FLUSH_N_INV);
|
||||
|
||||
/* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
|
||||
|
||||
/*
|
||||
* Only master CPU needs to execute rest of function:
|
||||
* - Assume SMP so all cores will have same cache config so
|
||||
* any geomtry checks will be same for all
|
||||
* - IOC setup / dma callbacks only need to be setup once
|
||||
* IOC Aperture size:
|
||||
* decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
|
||||
* TBD: fix for PGU + 1GB of low mem
|
||||
* TBD: fix for PAE
|
||||
*/
|
||||
if (cpu)
|
||||
return;
|
||||
ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
|
||||
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
|
||||
|
||||
/* Re-enable L1 dcache */
|
||||
__dc_enable();
|
||||
}
|
||||
|
||||
void __init arc_cache_init_master(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
|
||||
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
|
||||
|
|
@ -985,30 +1073,14 @@ void arc_cache_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (is_isa_arcv2() && l2_line_sz && !slc_enable) {
|
||||
/* Note that SLC disable not formally supported till HS 3.0 */
|
||||
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
|
||||
arc_slc_disable();
|
||||
|
||||
/* IM set : flush before invalidate */
|
||||
write_aux_reg(ARC_REG_SLC_CTRL,
|
||||
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM);
|
||||
|
||||
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
|
||||
|
||||
/* Important to wait for flush to complete */
|
||||
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
|
||||
write_aux_reg(ARC_REG_SLC_CTRL,
|
||||
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
|
||||
}
|
||||
if (is_isa_arcv2() && ioc_enable)
|
||||
arc_ioc_setup();
|
||||
|
||||
if (is_isa_arcv2() && ioc_enable) {
|
||||
/* IO coherency base - 0x8z */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
|
||||
/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
|
||||
/* Enable partial writes */
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
|
||||
/* Enable IO coherency */
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
|
||||
|
||||
__dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
|
||||
__dma_cache_inv = __dma_cache_inv_ioc;
|
||||
__dma_cache_wback = __dma_cache_wback_ioc;
|
||||
|
|
@ -1022,3 +1094,20 @@ void arc_cache_init(void)
|
|||
__dma_cache_wback = __dma_cache_wback_l1;
|
||||
}
|
||||
}
|
||||
|
||||
void __ref arc_cache_init(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
char str[256];
|
||||
|
||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||
|
||||
/*
|
||||
* Only master CPU needs to execute rest of function:
|
||||
* - Assume SMP so all cores will have same cache config so
|
||||
* any geomtry checks will be same for all
|
||||
* - IOC setup / dma callbacks only need to be setup once
|
||||
*/
|
||||
if (!cpu)
|
||||
arc_cache_init_master();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@ struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
|
|||
EXPORT_SYMBOL(node_data);
|
||||
#endif
|
||||
|
||||
long __init arc_get_mem_sz(void)
|
||||
{
|
||||
return low_mem_sz;
|
||||
}
|
||||
|
||||
/* User can over-ride above with "mem=nnn[KkMm]" in cmdline */
|
||||
static int __init setup_mem_sz(char *str)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -846,6 +846,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
|
|||
sun8i-a83t-allwinner-h8homlet-v2.dtb \
|
||||
sun8i-a83t-cubietruck-plus.dtb \
|
||||
sun8i-h3-bananapi-m2-plus.dtb \
|
||||
sun8i-h3-nanopi-m1.dtb \
|
||||
sun8i-h3-nanopi-neo.dtb \
|
||||
sun8i-h3-orangepi-2.dtb \
|
||||
sun8i-h3-orangepi-lite.dtb \
|
||||
|
|
|
|||
|
|
@ -170,7 +170,6 @@
|
|||
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
|
||||
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
|
||||
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
|
||||
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@
|
|||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x18000000 0x0011c40a>;
|
||||
ranges = <0x00000000 0x18000000 0x0011c40c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "m25p64";
|
||||
spi-max-frequency = <30000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
partition@0 {
|
||||
label = "U-Boot-SPL";
|
||||
|
|
|
|||
|
|
@ -1378,6 +1378,7 @@
|
|||
phy-names = "sata-phy";
|
||||
clocks = <&sata_ref_clk>;
|
||||
ti,hwmods = "sata";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
rtc: rtc@48838000 {
|
||||
|
|
|
|||
|
|
@ -75,6 +75,6 @@
|
|||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||
ti,min-output-imepdance;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -319,8 +319,6 @@
|
|||
compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-nitrogen6_max-sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -402,6 +400,8 @@
|
|||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
|
|
|
|||
|
|
@ -250,8 +250,6 @@
|
|||
compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6q-nitrogen6_som2-sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
|
|
@ -320,6 +318,8 @@
|
|||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sgtl5000>;
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@
|
|||
&mmc1 {
|
||||
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins &mmc1_cd>;
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
|
||||
cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
|
||||
vmmc-supply = <&vmmc1>;
|
||||
|
|
@ -193,7 +193,8 @@
|
|||
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
|
||||
OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 sdmmc1_wp*/
|
||||
OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */
|
||||
OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -242,12 +243,6 @@
|
|||
OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_cd: pinmux_mmc1_cd {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_WKUP_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -988,6 +988,7 @@
|
|||
phy-names = "sata-phy";
|
||||
clocks = <&sata_ref_clk>;
|
||||
ti,hwmods = "sata";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
dss: dss@58000000 {
|
||||
|
|
|
|||
|
|
@ -357,7 +357,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
|
|||
|
|
@ -140,6 +140,10 @@
|
|||
cpu-supply = <®_dcdc3>;
|
||||
};
|
||||
|
||||
&de {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -234,6 +234,7 @@
|
|||
de: display-engine {
|
||||
compatible = "allwinner,sun6i-a31-display-engine";
|
||||
allwinner,pipelines = <&fe0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
};
|
||||
|
||||
&pio {
|
||||
mmc2_pins_nrst: mmc2@0 {
|
||||
mmc2_pins_nrst: mmc2-rst-pin {
|
||||
allwinner,pins = "PC16";
|
||||
allwinner,function = "gpio_out";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
|
|
|
|||
|
|
@ -471,7 +471,7 @@ CONFIG_MESON_WATCHDOG=y
|
|||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_DIGICOLOR_WATCHDOG=y
|
||||
CONFIG_BCM2835_WDT=y
|
||||
CONFIG_BCM47XX_WATCHDOG=y
|
||||
CONFIG_BCM47XX_WDT=y
|
||||
CONFIG_BCM7038_WDT=m
|
||||
CONFIG_BCM_KONA_WDT=y
|
||||
CONFIG_MFD_ACT8945A=y
|
||||
|
|
@ -893,7 +893,7 @@ CONFIG_BCM2835_MBOX=y
|
|||
CONFIG_RASPBERRYPI_FIRMWARE=y
|
||||
CONFIG_EFI_VARS=m
|
||||
CONFIG_EFI_CAPSULE_LOADER=m
|
||||
CONFIG_CONFIG_BCM47XX_NVRAM=y
|
||||
CONFIG_BCM47XX_NVRAM=y
|
||||
CONFIG_BCM47XX_SPROM=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
|
|
|
|||
|
|
@ -86,9 +86,9 @@ CONFIG_IPV6_TUNNEL=m
|
|||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=m
|
||||
CONFIG_NF_CT_PROTO_SCTP=m
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=m
|
||||
CONFIG_NF_CT_PROTO_DCCP=y
|
||||
CONFIG_NF_CT_PROTO_SCTP=y
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=y
|
||||
CONFIG_NF_CONNTRACK_AMANDA=m
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_H323=m
|
||||
|
|
|
|||
|
|
@ -94,6 +94,9 @@
|
|||
#define ARM_CPU_XSCALE_ARCH_V2 0x4000
|
||||
#define ARM_CPU_XSCALE_ARCH_V3 0x6000
|
||||
|
||||
/* Qualcomm implemented cores */
|
||||
#define ARM_CPU_PART_SCORPION 0x510002d0
|
||||
|
||||
extern unsigned int processor_id;
|
||||
|
||||
#ifdef CONFIG_CPU_CP15
|
||||
|
|
|
|||
|
|
@ -54,6 +54,24 @@ static inline void *return_address(unsigned int level)
|
|||
|
||||
#define ftrace_return_address(n) return_address(n)
|
||||
|
||||
#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
|
||||
|
||||
static inline bool arch_syscall_match_sym_name(const char *sym,
|
||||
const char *name)
|
||||
{
|
||||
if (!strcmp(sym, "sys_mmap2"))
|
||||
sym = "sys_mmap_pgoff";
|
||||
else if (!strcmp(sym, "sys_statfs64_wrapper"))
|
||||
sym = "sys_statfs64";
|
||||
else if (!strcmp(sym, "sys_fstatfs64_wrapper"))
|
||||
sym = "sys_fstatfs64";
|
||||
else if (!strcmp(sym, "sys_arm_fadvise64_64"))
|
||||
sym = "sys_fadvise64_64";
|
||||
|
||||
/* Ignore case since sym may start with "SyS" instead of "sys" */
|
||||
return !strcasecmp(sym, name);
|
||||
}
|
||||
|
||||
#endif /* ifndef __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARM_FTRACE */
|
||||
|
|
|
|||
|
|
@ -80,6 +80,11 @@ static inline bool is_kernel_in_hyp_mode(void)
|
|||
return false;
|
||||
}
|
||||
|
||||
static inline bool has_vhe(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
/* The section containing the hypervisor idmap text */
|
||||
extern char __hyp_idmap_text_start[];
|
||||
extern char __hyp_idmap_text_end[];
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#ifndef _ASM_TYPES_H
|
||||
#define _ASM_TYPES_H
|
||||
#ifndef _UAPI_ASM_TYPES_H
|
||||
#define _UAPI_ASM_TYPES_H
|
||||
|
||||
#include <asm-generic/int-ll64.h>
|
||||
|
||||
|
|
@ -37,4 +37,4 @@
|
|||
#define __UINTPTR_TYPE__ unsigned long
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_TYPES_H */
|
||||
#endif /* _UAPI_ASM_TYPES_H */
|
||||
|
|
@ -1063,6 +1063,22 @@ static int __init arch_hw_breakpoint_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
|
||||
* whenever a WFI is issued, even if the core is not powered down, in
|
||||
* violation of the architecture. When DBGPRSR.SPD is set, accesses to
|
||||
* breakpoint and watchpoint registers are treated as undefined, so
|
||||
* this results in boot time and runtime failures when these are
|
||||
* accessed and we unexpectedly take a trap.
|
||||
*
|
||||
* It's not clear if/how this can be worked around, so we blacklist
|
||||
* Scorpion CPUs to avoid these issues.
|
||||
*/
|
||||
if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
|
||||
pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
has_ossr = core_has_os_save_restore();
|
||||
|
||||
/* Determine how many BRPs/WRPs are available. */
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
*/
|
||||
#include <linux/preempt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
|
@ -40,8 +41,11 @@ static inline void ipi_flush_tlb_mm(void *arg)
|
|||
static inline void ipi_flush_tlb_page(void *arg)
|
||||
{
|
||||
struct tlb_args *ta = (struct tlb_args *)arg;
|
||||
unsigned int __ua_flags = uaccess_save_and_enable();
|
||||
|
||||
local_flush_tlb_page(ta->ta_vma, ta->ta_start);
|
||||
|
||||
uaccess_restore(__ua_flags);
|
||||
}
|
||||
|
||||
static inline void ipi_flush_tlb_kernel_page(void *arg)
|
||||
|
|
@ -54,8 +58,11 @@ static inline void ipi_flush_tlb_kernel_page(void *arg)
|
|||
static inline void ipi_flush_tlb_range(void *arg)
|
||||
{
|
||||
struct tlb_args *ta = (struct tlb_args *)arg;
|
||||
unsigned int __ua_flags = uaccess_save_and_enable();
|
||||
|
||||
local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
|
||||
|
||||
uaccess_restore(__ua_flags);
|
||||
}
|
||||
|
||||
static inline void ipi_flush_tlb_kernel_range(void *arg)
|
||||
|
|
|
|||
|
|
@ -1099,6 +1099,9 @@ static void cpu_init_hyp_mode(void *dummy)
|
|||
__cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
|
||||
__cpu_init_stage2();
|
||||
|
||||
if (is_kernel_in_hyp_mode())
|
||||
kvm_timer_init_vhe();
|
||||
|
||||
kvm_arm_init_debug();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@
|
|||
#include "soc.h"
|
||||
|
||||
#define OMAP1_DMA_BASE (0xfffed800)
|
||||
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
|
||||
|
||||
static u32 enable_1510_mode;
|
||||
|
||||
|
|
@ -348,8 +347,6 @@ static int __init omap1_system_dma_init(void)
|
|||
goto exit_iounmap;
|
||||
}
|
||||
|
||||
d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
|
||||
|
||||
/* Valid attributes for omap1 plus processors */
|
||||
if (cpu_is_omap15xx())
|
||||
d->dev_caps = ENABLE_1510_MODE;
|
||||
|
|
@ -366,13 +363,14 @@ static int __init omap1_system_dma_init(void)
|
|||
d->dev_caps |= CLEAR_CSR_ON_READ;
|
||||
d->dev_caps |= IS_WORD_16;
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
d->chan_count = 9;
|
||||
else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
|
||||
if (!(d->dev_caps & ENABLE_1510_MODE))
|
||||
d->chan_count = 16;
|
||||
/* available logical channels */
|
||||
if (cpu_is_omap15xx()) {
|
||||
d->lch_count = 9;
|
||||
} else {
|
||||
if (d->dev_caps & ENABLE_1510_MODE)
|
||||
d->lch_count = 9;
|
||||
else
|
||||
d->chan_count = 9;
|
||||
d->lch_count = 16;
|
||||
}
|
||||
|
||||
p = dma_plat_info;
|
||||
|
|
|
|||
|
|
@ -161,7 +161,7 @@ static struct ti_st_plat_data wilink7_pdata = {
|
|||
.nshutdown_gpio = 162,
|
||||
.dev_name = "/dev/ttyO1",
|
||||
.flow_cntrl = 1,
|
||||
.baud_rate = 300000,
|
||||
.baud_rate = 3000000,
|
||||
};
|
||||
|
||||
static struct platform_device wl128x_device = {
|
||||
|
|
|
|||
|
|
@ -134,8 +134,8 @@ bool prcmu_pending_irq(void)
|
|||
*/
|
||||
bool prcmu_is_cpu_in_wfi(int cpu)
|
||||
{
|
||||
return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
|
||||
PRCM_ARM_WFI_STANDBY_WFI0;
|
||||
return readl(PRCM_ARM_WFI_STANDBY) &
|
||||
(cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : PRCM_ARM_WFI_STANDBY_WFI0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -137,6 +137,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&scpi_clocks {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
mboxes = <&mailbox 1 &mailbox 2>;
|
||||
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
||||
|
||||
clocks {
|
||||
scpi_clocks: clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: scpi_clocks@0 {
|
||||
|
|
|
|||
|
|
@ -1367,7 +1367,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x40000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@
|
|||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
amba_apu {
|
||||
amba_apu: amba_apu@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -175,7 +175,7 @@
|
|||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 4>;
|
||||
|
|
@ -185,7 +185,7 @@
|
|||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 18 4>;
|
||||
|
|
|
|||
|
|
@ -193,15 +193,16 @@ AES_ENTRY(aes_cbc_encrypt)
|
|||
cbz w6, .Lcbcencloop
|
||||
|
||||
ld1 {v0.16b}, [x5] /* get iv */
|
||||
enc_prepare w3, x2, x5
|
||||
enc_prepare w3, x2, x6
|
||||
|
||||
.Lcbcencloop:
|
||||
ld1 {v1.16b}, [x1], #16 /* get next pt block */
|
||||
eor v0.16b, v0.16b, v1.16b /* ..and xor with iv */
|
||||
encrypt_block v0, w3, x2, x5, w6
|
||||
encrypt_block v0, w3, x2, x6, w7
|
||||
st1 {v0.16b}, [x0], #16
|
||||
subs w4, w4, #1
|
||||
bne .Lcbcencloop
|
||||
st1 {v0.16b}, [x5] /* return iv */
|
||||
ret
|
||||
AES_ENDPROC(aes_cbc_encrypt)
|
||||
|
||||
|
|
@ -211,7 +212,7 @@ AES_ENTRY(aes_cbc_decrypt)
|
|||
cbz w6, .LcbcdecloopNx
|
||||
|
||||
ld1 {v7.16b}, [x5] /* get iv */
|
||||
dec_prepare w3, x2, x5
|
||||
dec_prepare w3, x2, x6
|
||||
|
||||
.LcbcdecloopNx:
|
||||
#if INTERLEAVE >= 2
|
||||
|
|
@ -248,7 +249,7 @@ AES_ENTRY(aes_cbc_decrypt)
|
|||
.Lcbcdecloop:
|
||||
ld1 {v1.16b}, [x1], #16 /* get next ct block */
|
||||
mov v0.16b, v1.16b /* ...and copy to v0 */
|
||||
decrypt_block v0, w3, x2, x5, w6
|
||||
decrypt_block v0, w3, x2, x6, w7
|
||||
eor v0.16b, v0.16b, v7.16b /* xor with iv => pt */
|
||||
mov v7.16b, v1.16b /* ct is next iv */
|
||||
st1 {v0.16b}, [x0], #16
|
||||
|
|
@ -256,6 +257,7 @@ AES_ENTRY(aes_cbc_decrypt)
|
|||
bne .Lcbcdecloop
|
||||
.Lcbcdecout:
|
||||
FRAME_POP
|
||||
st1 {v7.16b}, [x5] /* return iv */
|
||||
ret
|
||||
AES_ENDPROC(aes_cbc_decrypt)
|
||||
|
||||
|
|
@ -267,24 +269,15 @@ AES_ENDPROC(aes_cbc_decrypt)
|
|||
|
||||
AES_ENTRY(aes_ctr_encrypt)
|
||||
FRAME_PUSH
|
||||
cbnz w6, .Lctrfirst /* 1st time around? */
|
||||
umov x5, v4.d[1] /* keep swabbed ctr in reg */
|
||||
rev x5, x5
|
||||
#if INTERLEAVE >= 2
|
||||
cmn w5, w4 /* 32 bit overflow? */
|
||||
bcs .Lctrinc
|
||||
add x5, x5, #1 /* increment BE ctr */
|
||||
b .LctrincNx
|
||||
#else
|
||||
b .Lctrinc
|
||||
#endif
|
||||
.Lctrfirst:
|
||||
cbz w6, .Lctrnotfirst /* 1st time around? */
|
||||
enc_prepare w3, x2, x6
|
||||
ld1 {v4.16b}, [x5]
|
||||
umov x5, v4.d[1] /* keep swabbed ctr in reg */
|
||||
rev x5, x5
|
||||
|
||||
.Lctrnotfirst:
|
||||
umov x8, v4.d[1] /* keep swabbed ctr in reg */
|
||||
rev x8, x8
|
||||
#if INTERLEAVE >= 2
|
||||
cmn w5, w4 /* 32 bit overflow? */
|
||||
cmn w8, w4 /* 32 bit overflow? */
|
||||
bcs .Lctrloop
|
||||
.LctrloopNx:
|
||||
subs w4, w4, #INTERLEAVE
|
||||
|
|
@ -292,11 +285,11 @@ AES_ENTRY(aes_ctr_encrypt)
|
|||
#if INTERLEAVE == 2
|
||||
mov v0.8b, v4.8b
|
||||
mov v1.8b, v4.8b
|
||||
rev x7, x5
|
||||
add x5, x5, #1
|
||||
rev x7, x8
|
||||
add x8, x8, #1
|
||||
ins v0.d[1], x7
|
||||
rev x7, x5
|
||||
add x5, x5, #1
|
||||
rev x7, x8
|
||||
add x8, x8, #1
|
||||
ins v1.d[1], x7
|
||||
ld1 {v2.16b-v3.16b}, [x1], #32 /* get 2 input blocks */
|
||||
do_encrypt_block2x
|
||||
|
|
@ -305,7 +298,7 @@ AES_ENTRY(aes_ctr_encrypt)
|
|||
st1 {v0.16b-v1.16b}, [x0], #32
|
||||
#else
|
||||
ldr q8, =0x30000000200000001 /* addends 1,2,3[,0] */
|
||||
dup v7.4s, w5
|
||||
dup v7.4s, w8
|
||||
mov v0.16b, v4.16b
|
||||
add v7.4s, v7.4s, v8.4s
|
||||
mov v1.16b, v4.16b
|
||||
|
|
@ -323,18 +316,12 @@ AES_ENTRY(aes_ctr_encrypt)
|
|||
eor v2.16b, v7.16b, v2.16b
|
||||
eor v3.16b, v5.16b, v3.16b
|
||||
st1 {v0.16b-v3.16b}, [x0], #64
|
||||
add x5, x5, #INTERLEAVE
|
||||
add x8, x8, #INTERLEAVE
|
||||
#endif
|
||||
cbz w4, .LctroutNx
|
||||
.LctrincNx:
|
||||
rev x7, x5
|
||||
rev x7, x8
|
||||
ins v4.d[1], x7
|
||||
cbz w4, .Lctrout
|
||||
b .LctrloopNx
|
||||
.LctroutNx:
|
||||
sub x5, x5, #1
|
||||
rev x7, x5
|
||||
ins v4.d[1], x7
|
||||
b .Lctrout
|
||||
.Lctr1x:
|
||||
adds w4, w4, #INTERLEAVE
|
||||
beq .Lctrout
|
||||
|
|
@ -342,30 +329,39 @@ AES_ENTRY(aes_ctr_encrypt)
|
|||
.Lctrloop:
|
||||
mov v0.16b, v4.16b
|
||||
encrypt_block v0, w3, x2, x6, w7
|
||||
|
||||
adds x8, x8, #1 /* increment BE ctr */
|
||||
rev x7, x8
|
||||
ins v4.d[1], x7
|
||||
bcs .Lctrcarry /* overflow? */
|
||||
|
||||
.Lctrcarrydone:
|
||||
subs w4, w4, #1
|
||||
bmi .Lctrhalfblock /* blocks < 0 means 1/2 block */
|
||||
ld1 {v3.16b}, [x1], #16
|
||||
eor v3.16b, v0.16b, v3.16b
|
||||
st1 {v3.16b}, [x0], #16
|
||||
beq .Lctrout
|
||||
.Lctrinc:
|
||||
adds x5, x5, #1 /* increment BE ctr */
|
||||
rev x7, x5
|
||||
ins v4.d[1], x7
|
||||
bcc .Lctrloop /* no overflow? */
|
||||
bne .Lctrloop
|
||||
|
||||
.Lctrout:
|
||||
st1 {v4.16b}, [x5] /* return next CTR value */
|
||||
FRAME_POP
|
||||
ret
|
||||
|
||||
.Lctrhalfblock:
|
||||
ld1 {v3.8b}, [x1]
|
||||
eor v3.8b, v0.8b, v3.8b
|
||||
st1 {v3.8b}, [x0]
|
||||
FRAME_POP
|
||||
ret
|
||||
|
||||
.Lctrcarry:
|
||||
umov x7, v4.d[0] /* load upper word of ctr */
|
||||
rev x7, x7 /* ... to handle the carry */
|
||||
add x7, x7, #1
|
||||
rev x7, x7
|
||||
ins v4.d[0], x7
|
||||
b .Lctrloop
|
||||
.Lctrhalfblock:
|
||||
ld1 {v3.8b}, [x1]
|
||||
eor v3.8b, v0.8b, v3.8b
|
||||
st1 {v3.8b}, [x0]
|
||||
.Lctrout:
|
||||
FRAME_POP
|
||||
ret
|
||||
b .Lctrcarrydone
|
||||
AES_ENDPROC(aes_ctr_encrypt)
|
||||
.ltorg
|
||||
|
||||
|
|
|
|||
|
|
@ -222,7 +222,7 @@ static inline void *phys_to_virt(phys_addr_t x)
|
|||
#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
|
||||
#else
|
||||
#define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page))
|
||||
#define __page_to_voff(page) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
|
||||
#define __page_to_voff(kaddr) (((u64)(kaddr) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
|
||||
|
||||
#define page_to_virt(page) ((void *)((__page_to_voff(page)) | PAGE_OFFSET))
|
||||
#define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) | VMEMMAP_START))
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#include <asm/ptrace.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/sysreg.h>
|
||||
#include <asm/cpufeature.h>
|
||||
|
||||
/*
|
||||
* __boot_cpu_mode records what mode CPUs were booted in.
|
||||
|
|
@ -80,6 +81,14 @@ static inline bool is_kernel_in_hyp_mode(void)
|
|||
return read_sysreg(CurrentEL) == CurrentEL_EL2;
|
||||
}
|
||||
|
||||
static inline bool has_vhe(void)
|
||||
{
|
||||
if (cpus_have_const_cap(ARM64_HAS_VIRT_HOST_EXTN))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64_VHE
|
||||
extern void verify_cpu_run_el(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ struct user_fpsimd_state {
|
|||
__uint128_t vregs[32];
|
||||
__u32 fpsr;
|
||||
__u32 fpcr;
|
||||
__u32 __reserved[2];
|
||||
};
|
||||
|
||||
struct user_hwdebug_state {
|
||||
|
|
|
|||
|
|
@ -683,7 +683,7 @@ el0_inv:
|
|||
mov x0, sp
|
||||
mov x1, #BAD_SYNC
|
||||
mov x2, x25
|
||||
bl bad_mode
|
||||
bl bad_el0_sync
|
||||
b ret_to_user
|
||||
ENDPROC(el0_sync)
|
||||
|
||||
|
|
|
|||
|
|
@ -551,6 +551,8 @@ static int hw_break_set(struct task_struct *target,
|
|||
/* (address, ctrl) registers */
|
||||
limit = regset->n * regset->size;
|
||||
while (count && offset < limit) {
|
||||
if (count < PTRACE_HBP_ADDR_SZ)
|
||||
return -EINVAL;
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr,
|
||||
offset, offset + PTRACE_HBP_ADDR_SZ);
|
||||
if (ret)
|
||||
|
|
@ -560,6 +562,8 @@ static int hw_break_set(struct task_struct *target,
|
|||
return ret;
|
||||
offset += PTRACE_HBP_ADDR_SZ;
|
||||
|
||||
if (!count)
|
||||
break;
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl,
|
||||
offset, offset + PTRACE_HBP_CTRL_SZ);
|
||||
if (ret)
|
||||
|
|
@ -596,7 +600,7 @@ static int gpr_set(struct task_struct *target, const struct user_regset *regset,
|
|||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
int ret;
|
||||
struct user_pt_regs newregs;
|
||||
struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
|
||||
if (ret)
|
||||
|
|
@ -626,7 +630,8 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
|
|||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
int ret;
|
||||
struct user_fpsimd_state newstate;
|
||||
struct user_fpsimd_state newstate =
|
||||
target->thread.fpsimd_state.user_fpsimd;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
|
||||
if (ret)
|
||||
|
|
@ -650,7 +655,7 @@ static int tls_set(struct task_struct *target, const struct user_regset *regset,
|
|||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
int ret;
|
||||
unsigned long tls;
|
||||
unsigned long tls = target->thread.tp_value;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
|
||||
if (ret)
|
||||
|
|
@ -676,7 +681,8 @@ static int system_call_set(struct task_struct *target,
|
|||
unsigned int pos, unsigned int count,
|
||||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
int syscallno, ret;
|
||||
int syscallno = task_pt_regs(target)->syscallno;
|
||||
int ret;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1);
|
||||
if (ret)
|
||||
|
|
@ -948,7 +954,7 @@ static int compat_tls_set(struct task_struct *target,
|
|||
const void __user *ubuf)
|
||||
{
|
||||
int ret;
|
||||
compat_ulong_t tls;
|
||||
compat_ulong_t tls = target->thread.tp_value;
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/init.h>
|
||||
|
|
@ -209,7 +210,12 @@ static struct notifier_block init_cpu_capacity_notifier = {
|
|||
|
||||
static int __init register_cpufreq_notifier(void)
|
||||
{
|
||||
if (cap_parsing_failed)
|
||||
/*
|
||||
* on ACPI-based systems we need to use the default cpu capacity
|
||||
* until we have the necessary code to parse the cpu capacity, so
|
||||
* skip registering cpufreq notifier.
|
||||
*/
|
||||
if (!acpi_disabled || cap_parsing_failed)
|
||||
return -EINVAL;
|
||||
|
||||
if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL)) {
|
||||
|
|
|
|||
|
|
@ -604,17 +604,34 @@ const char *esr_get_class_string(u32 esr)
|
|||
}
|
||||
|
||||
/*
|
||||
* bad_mode handles the impossible case in the exception vector.
|
||||
* bad_mode handles the impossible case in the exception vector. This is always
|
||||
* fatal.
|
||||
*/
|
||||
asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
|
||||
{
|
||||
siginfo_t info;
|
||||
void __user *pc = (void __user *)instruction_pointer(regs);
|
||||
console_verbose();
|
||||
|
||||
pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
|
||||
handler[reason], smp_processor_id(), esr,
|
||||
esr_get_class_string(esr));
|
||||
|
||||
die("Oops - bad mode", regs, 0);
|
||||
local_irq_disable();
|
||||
panic("bad mode");
|
||||
}
|
||||
|
||||
/*
|
||||
* bad_el0_sync handles unexpected, but potentially recoverable synchronous
|
||||
* exceptions taken from EL0. Unlike bad_mode, this returns.
|
||||
*/
|
||||
asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
|
||||
{
|
||||
siginfo_t info;
|
||||
void __user *pc = (void __user *)instruction_pointer(regs);
|
||||
console_verbose();
|
||||
|
||||
pr_crit("Bad EL0 synchronous exception detected on CPU%d, code 0x%08x -- %s\n",
|
||||
smp_processor_id(), esr, esr_get_class_string(esr));
|
||||
__show_regs(regs);
|
||||
|
||||
info.si_signo = SIGILL;
|
||||
|
|
@ -622,7 +639,10 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
|
|||
info.si_code = ILL_ILLOPC;
|
||||
info.si_addr = pc;
|
||||
|
||||
arm64_notify_die("Oops - bad mode", regs, &info, 0);
|
||||
current->thread.fault_address = 0;
|
||||
current->thread.fault_code = 0;
|
||||
|
||||
force_sig_info(info.si_signo, &info, current);
|
||||
}
|
||||
|
||||
void __pte_error(const char *file, int line, unsigned long val)
|
||||
|
|
|
|||
|
|
@ -404,6 +404,8 @@ void __init mem_init(void)
|
|||
if (swiotlb_force == SWIOTLB_FORCE ||
|
||||
max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
|
||||
swiotlb_init(1);
|
||||
else
|
||||
swiotlb_force = SWIOTLB_NO_FORCE;
|
||||
|
||||
set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
|
||||
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ static inline void atomic64_dec(atomic64_t *v)
|
|||
#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
|
||||
#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
|
||||
#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0)
|
||||
|
||||
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
|
||||
|
||||
#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
|
||||
#define atomic_xchg(v, new) (xchg(&(v)->counter, new))
|
||||
|
|
@ -161,6 +161,39 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
|
|||
return c;
|
||||
}
|
||||
|
||||
static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)
|
||||
{
|
||||
long long c, old;
|
||||
|
||||
c = atomic64_read(v);
|
||||
for (;;) {
|
||||
if (unlikely(c == u))
|
||||
break;
|
||||
old = atomic64_cmpxchg(v, c, c + i);
|
||||
if (likely(old == c))
|
||||
break;
|
||||
c = old;
|
||||
}
|
||||
return c != u;
|
||||
}
|
||||
|
||||
static inline long long atomic64_dec_if_positive(atomic64_t *v)
|
||||
{
|
||||
long long c, old, dec;
|
||||
|
||||
c = atomic64_read(v);
|
||||
for (;;) {
|
||||
dec = c - 1;
|
||||
if (unlikely(dec < 0))
|
||||
break;
|
||||
old = atomic64_cmpxchg((v), c, dec);
|
||||
if (likely(old == c))
|
||||
break;
|
||||
c = old;
|
||||
}
|
||||
return dec;
|
||||
}
|
||||
|
||||
#define ATOMIC_OP(op) \
|
||||
static inline int atomic_fetch_##op(int i, atomic_t *v) \
|
||||
{ \
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
struct task_struct;
|
||||
struct thread_struct;
|
||||
|
||||
#if !defined(CONFIG_LAZY_SAVE_FPU)
|
||||
#if defined(CONFIG_FPU) && !defined(CONFIG_LAZY_SAVE_FPU)
|
||||
struct fpu_state_struct;
|
||||
extern asmlinkage void fpu_save(struct fpu_state_struct *);
|
||||
#define switch_fpu(prev, next) \
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#endif
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/types.h> /* for BITS_PER_LONG/SHIFT_PER_LONG */
|
||||
#include <asm/types.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/barrier.h>
|
||||
#include <linux/atomic.h>
|
||||
|
|
@ -17,6 +17,12 @@
|
|||
* to include/asm-i386/bitops.h or kerneldoc
|
||||
*/
|
||||
|
||||
#if __BITS_PER_LONG == 64
|
||||
#define SHIFT_PER_LONG 6
|
||||
#else
|
||||
#define SHIFT_PER_LONG 5
|
||||
#endif
|
||||
|
||||
#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -3,10 +3,8 @@
|
|||
|
||||
#if defined(__LP64__)
|
||||
#define __BITS_PER_LONG 64
|
||||
#define SHIFT_PER_LONG 6
|
||||
#else
|
||||
#define __BITS_PER_LONG 32
|
||||
#define SHIFT_PER_LONG 5
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bitsperlong.h>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef _PARISC_SWAB_H
|
||||
#define _PARISC_SWAB_H
|
||||
|
||||
#include <asm/bitsperlong.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
|
|
@ -38,7 +39,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
|||
}
|
||||
#define __arch_swab32 __arch_swab32
|
||||
|
||||
#if BITS_PER_LONG > 32
|
||||
#if __BITS_PER_LONG > 32
|
||||
/*
|
||||
** From "PA-RISC 2.0 Architecture", HP Professional Books.
|
||||
** See Appendix I page 8 , "Endian Byte Swapping".
|
||||
|
|
@ -61,6 +62,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
|
|||
return x;
|
||||
}
|
||||
#define __arch_swab64 __arch_swab64
|
||||
#endif /* BITS_PER_LONG > 32 */
|
||||
#endif /* __BITS_PER_LONG > 32 */
|
||||
|
||||
#endif /* _PARISC_SWAB_H */
|
||||
|
|
|
|||
|
|
@ -164,7 +164,6 @@ config PPC
|
|||
select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE
|
||||
select HAVE_ARCH_HARDENED_USERCOPY
|
||||
select HAVE_KERNEL_GZIP
|
||||
select HAVE_CC_STACKPROTECTOR
|
||||
|
||||
config GENERIC_CSUM
|
||||
def_bool CPU_LITTLE_ENDIAN
|
||||
|
|
@ -484,6 +483,7 @@ config RELOCATABLE
|
|||
bool "Build a relocatable kernel"
|
||||
depends on (PPC64 && !COMPILE_TEST) || (FLATMEM && (44x || FSL_BOOKE))
|
||||
select NONSTATIC_KERNEL
|
||||
select MODULE_REL_CRCS if MODVERSIONS
|
||||
help
|
||||
This builds a kernel image that is capable of running at the
|
||||
location the kernel is loaded at. For ppc32, there is no any
|
||||
|
|
|
|||
|
|
@ -36,12 +36,13 @@
|
|||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
static inline int hash__hugepd_ok(hugepd_t hpd)
|
||||
{
|
||||
unsigned long hpdval = hpd_val(hpd);
|
||||
/*
|
||||
* if it is not a pte and have hugepd shift mask
|
||||
* set, then it is a hugepd directory pointer
|
||||
*/
|
||||
if (!(hpd.pd & _PAGE_PTE) &&
|
||||
((hpd.pd & HUGEPD_SHIFT_MASK) != 0))
|
||||
if (!(hpdval & _PAGE_PTE) &&
|
||||
((hpdval & HUGEPD_SHIFT_MASK) != 0))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -201,6 +201,10 @@ extern int __meminit hash__vmemmap_create_mapping(unsigned long start,
|
|||
unsigned long phys);
|
||||
extern void hash__vmemmap_remove_mapping(unsigned long start,
|
||||
unsigned long page_size);
|
||||
|
||||
int hash__create_section_mapping(unsigned long start, unsigned long end);
|
||||
int hash__remove_section_mapping(unsigned long start, unsigned long end);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,9 @@ static __always_inline bool cpu_has_feature(unsigned long feature)
|
|||
{
|
||||
int i;
|
||||
|
||||
#ifndef __clang__ /* clang can't cope with this */
|
||||
BUILD_BUG_ON(!__builtin_constant_p(feature));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
|
||||
if (!static_key_initialized) {
|
||||
|
|
|
|||
|
|
@ -21,12 +21,12 @@ static inline pte_t *hugepd_page(hugepd_t hpd)
|
|||
* We have only four bits to encode, MMU page size
|
||||
*/
|
||||
BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf);
|
||||
return __va(hpd.pd & HUGEPD_ADDR_MASK);
|
||||
return __va(hpd_val(hpd) & HUGEPD_ADDR_MASK);
|
||||
}
|
||||
|
||||
static inline unsigned int hugepd_mmu_psize(hugepd_t hpd)
|
||||
{
|
||||
return (hpd.pd & HUGEPD_SHIFT_MASK) >> 2;
|
||||
return (hpd_val(hpd) & HUGEPD_SHIFT_MASK) >> 2;
|
||||
}
|
||||
|
||||
static inline unsigned int hugepd_shift(hugepd_t hpd)
|
||||
|
|
@ -52,18 +52,20 @@ static inline pte_t *hugepd_page(hugepd_t hpd)
|
|||
{
|
||||
BUG_ON(!hugepd_ok(hpd));
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
return (pte_t *)__va(hpd.pd & ~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK));
|
||||
return (pte_t *)__va(hpd_val(hpd) &
|
||||
~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK));
|
||||
#else
|
||||
return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
|
||||
return (pte_t *)((hpd_val(hpd) &
|
||||
~HUGEPD_SHIFT_MASK) | PD_HUGE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline unsigned int hugepd_shift(hugepd_t hpd)
|
||||
{
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
return ((hpd.pd & _PMD_PAGE_MASK) >> 1) + 17;
|
||||
return ((hpd_val(hpd) & _PMD_PAGE_MASK) >> 1) + 17;
|
||||
#else
|
||||
return hpd.pd & HUGEPD_SHIFT_MASK;
|
||||
return hpd_val(hpd) & HUGEPD_SHIFT_MASK;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -160,7 +160,9 @@ static __always_inline bool mmu_has_feature(unsigned long feature)
|
|||
{
|
||||
int i;
|
||||
|
||||
#ifndef __clang__ /* clang can't cope with this */
|
||||
BUILD_BUG_ON(!__builtin_constant_p(feature));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
|
||||
if (!static_key_initialized) {
|
||||
|
|
|
|||
|
|
@ -90,9 +90,5 @@ static inline int module_finalize_ftrace(struct module *mod, const Elf_Shdr *sec
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MODVERSIONS) && defined(CONFIG_PPC64)
|
||||
#define ARCH_RELOCATES_KCRCTAB
|
||||
#define reloc_start PHYSICAL_START
|
||||
#endif
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_MODULE_H */
|
||||
|
|
|
|||
|
|
@ -227,9 +227,10 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|||
static inline int hugepd_ok(hugepd_t hpd)
|
||||
{
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
return ((hpd.pd & 0x4) != 0);
|
||||
return ((hpd_val(hpd) & 0x4) != 0);
|
||||
#else
|
||||
return (hpd.pd > 0);
|
||||
/* We clear the top bit to indicate hugepd */
|
||||
return ((hpd_val(hpd) & PD_HUGE) == 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -294,15 +294,12 @@ extern long long virt_phys_offset;
|
|||
#include <asm/pgtable-types.h>
|
||||
#endif
|
||||
|
||||
typedef struct { signed long pd; } hugepd_t;
|
||||
|
||||
#ifndef CONFIG_HUGETLB_PAGE
|
||||
#define is_hugepd(pdep) (0)
|
||||
#define pgd_huge(pgd) (0)
|
||||
#endif /* CONFIG_HUGETLB_PAGE */
|
||||
|
||||
#define __hugepd(x) ((hugepd_t) { (x) })
|
||||
|
||||
struct page;
|
||||
extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
|
||||
extern void copy_user_page(void *to, void *from, unsigned long vaddr,
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ struct power_pmu {
|
|||
#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
|
||||
#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
|
||||
#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
|
||||
#define PPMU_NO_SIAR 0x00000100 /* Do not use SIAR */
|
||||
|
||||
/*
|
||||
* Values for flags to get_alternatives()
|
||||
|
|
|
|||
|
|
@ -104,4 +104,12 @@ static inline bool pmd_xchg(pmd_t *pmdp, pmd_t old, pmd_t new)
|
|||
return pmd_raw(old) == prev;
|
||||
}
|
||||
|
||||
typedef struct { __be64 pdbe; } hugepd_t;
|
||||
#define __hugepd(x) ((hugepd_t) { cpu_to_be64(x) })
|
||||
|
||||
static inline unsigned long hpd_val(hugepd_t x)
|
||||
{
|
||||
return be64_to_cpu(x.pdbe);
|
||||
}
|
||||
|
||||
#endif /* _ASM_POWERPC_PGTABLE_BE_TYPES_H */
|
||||
|
|
|
|||
|
|
@ -66,4 +66,11 @@ static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new)
|
|||
}
|
||||
#endif
|
||||
|
||||
typedef struct { unsigned long pd; } hugepd_t;
|
||||
#define __hugepd(x) ((hugepd_t) { (x) })
|
||||
static inline unsigned long hpd_val(hugepd_t x)
|
||||
{
|
||||
return x.pd;
|
||||
}
|
||||
|
||||
#endif /* _ASM_POWERPC_PGTABLE_TYPES_H */
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@
|
|||
#define PPC_INST_MCRXR 0x7c000400
|
||||
#define PPC_INST_MCRXR_MASK 0xfc0007fe
|
||||
#define PPC_INST_MFSPR_PVR 0x7c1f42a6
|
||||
#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
|
||||
#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
|
||||
#define PPC_INST_MFTMR 0x7c0002dc
|
||||
#define PPC_INST_MSGSND 0x7c00019c
|
||||
#define PPC_INST_MSGCLR 0x7c0001dc
|
||||
|
|
@ -174,13 +174,13 @@
|
|||
#define PPC_INST_RFDI 0x4c00004e
|
||||
#define PPC_INST_RFMCI 0x4c00004c
|
||||
#define PPC_INST_MFSPR_DSCR 0x7c1102a6
|
||||
#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
|
||||
#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
|
||||
#define PPC_INST_MTSPR_DSCR 0x7c1103a6
|
||||
#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
|
||||
#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
|
||||
#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
|
||||
#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
|
||||
#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
|
||||
#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
|
||||
#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
|
||||
#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
|
||||
#define PPC_INST_MFVSRD 0x7c000066
|
||||
#define PPC_INST_MTVSRD 0x7c000166
|
||||
#define PPC_INST_SLBFEE 0x7c0007a7
|
||||
|
|
|
|||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* GCC stack protector support.
|
||||
*
|
||||
* Stack protector works by putting predefined pattern at the start of
|
||||
* the stack frame and verifying that it hasn't been overwritten when
|
||||
* returning from the function. The pattern is called stack canary
|
||||
* and gcc expects it to be defined by a global variable called
|
||||
* "__stack_chk_guard" on PPC. This unfortunately means that on SMP
|
||||
* we cannot have a different canary value per task.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_STACKPROTECTOR_H
|
||||
#define _ASM_STACKPROTECTOR_H
|
||||
|
||||
#include <linux/random.h>
|
||||
#include <linux/version.h>
|
||||
#include <asm/reg.h>
|
||||
|
||||
extern unsigned long __stack_chk_guard;
|
||||
|
||||
/*
|
||||
* Initialize the stackprotector canary value.
|
||||
*
|
||||
* NOTE: this must only be called from functions that never return,
|
||||
* and it must always be inlined.
|
||||
*/
|
||||
static __always_inline void boot_init_stack_canary(void)
|
||||
{
|
||||
unsigned long canary;
|
||||
|
||||
/* Try to get a semi random initial value. */
|
||||
get_random_bytes(&canary, sizeof(canary));
|
||||
canary ^= mftb();
|
||||
canary ^= LINUX_VERSION_CODE;
|
||||
|
||||
current->stack_canary = canary;
|
||||
__stack_chk_guard = current->stack_canary;
|
||||
}
|
||||
|
||||
#endif /* _ASM_STACKPROTECTOR_H */
|
||||
|
|
@ -19,10 +19,6 @@ CFLAGS_init.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
|
|||
CFLAGS_btext.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
|
||||
CFLAGS_prom.o += $(DISABLE_LATENT_ENTROPY_PLUGIN)
|
||||
|
||||
# -fstack-protector triggers protection checks in this code,
|
||||
# but it is being used too early to link to meaningful stack_chk logic.
|
||||
CFLAGS_prom_init.o += $(call cc-option, -fno-stack-protector)
|
||||
|
||||
ifdef CONFIG_FUNCTION_TRACER
|
||||
# Do not trace early boot code
|
||||
CFLAGS_REMOVE_cputable.o = -mno-sched-epilog $(CC_FLAGS_FTRACE)
|
||||
|
|
|
|||
|
|
@ -91,9 +91,6 @@ int main(void)
|
|||
DEFINE(TI_livepatch_sp, offsetof(struct thread_info, livepatch_sp));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CC_STACKPROTECTOR
|
||||
DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
|
||||
#endif
|
||||
DEFINE(KSP, offsetof(struct thread_struct, ksp));
|
||||
DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
|
||||
#ifdef CONFIG_BOOKE
|
||||
|
|
|
|||
|
|
@ -298,9 +298,17 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
|
|||
*
|
||||
* For pHyp, we have to enable IO for log retrieval. Otherwise,
|
||||
* 0xFF's is always returned from PCI config space.
|
||||
*
|
||||
* When the @severity is EEH_LOG_PERM, the PE is going to be
|
||||
* removed. Prior to that, the drivers for devices included in
|
||||
* the PE will be closed. The drivers rely on working IO path
|
||||
* to bring the devices to quiet state. Otherwise, PCI traffic
|
||||
* from those devices after they are removed is like to cause
|
||||
* another unexpected EEH error.
|
||||
*/
|
||||
if (!(pe->type & EEH_PE_PHB)) {
|
||||
if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG))
|
||||
if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
|
||||
severity == EEH_LOG_PERM)
|
||||
eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -545,7 +545,7 @@ static void *eeh_pe_detach_dev(void *data, void *userdata)
|
|||
static void *__eeh_clear_pe_frozen_state(void *data, void *flag)
|
||||
{
|
||||
struct eeh_pe *pe = (struct eeh_pe *)data;
|
||||
bool *clear_sw_state = flag;
|
||||
bool clear_sw_state = *(bool *)flag;
|
||||
int i, rc = 1;
|
||||
|
||||
for (i = 0; rc && i < 3; i++)
|
||||
|
|
|
|||
|
|
@ -674,11 +674,7 @@ BEGIN_FTR_SECTION
|
|||
mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_SPE)
|
||||
#endif /* CONFIG_SPE */
|
||||
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
|
||||
lwz r0,TSK_STACK_CANARY(r2)
|
||||
lis r4,__stack_chk_guard@ha
|
||||
stw r0,__stack_chk_guard@l(r4)
|
||||
#endif
|
||||
|
||||
lwz r0,_CCR(r1)
|
||||
mtcrf 0xFF,r0
|
||||
/* r3-r12 are destroyed -- Cort */
|
||||
|
|
|
|||
|
|
@ -286,14 +286,6 @@ static void dedotify_versions(struct modversion_info *vers,
|
|||
for (end = (void *)vers + size; vers < end; vers++)
|
||||
if (vers->name[0] == '.') {
|
||||
memmove(vers->name, vers->name+1, strlen(vers->name));
|
||||
#ifdef ARCH_RELOCATES_KCRCTAB
|
||||
/* The TOC symbol has no CRC computed. To avoid CRC
|
||||
* check failing, we must force it to the expected
|
||||
* value (see CRC check in module.c).
|
||||
*/
|
||||
if (!strcmp(vers->name, "TOC."))
|
||||
vers->crc = -(unsigned long)reloc_start;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -64,12 +64,6 @@
|
|||
#include <linux/kprobes.h>
|
||||
#include <linux/kdebug.h>
|
||||
|
||||
#ifdef CONFIG_CC_STACKPROTECTOR
|
||||
#include <linux/stackprotector.h>
|
||||
unsigned long __stack_chk_guard __read_mostly;
|
||||
EXPORT_SYMBOL(__stack_chk_guard);
|
||||
#endif
|
||||
|
||||
/* Transactional Memory debug */
|
||||
#ifdef TM_DEBUG_SW
|
||||
#define TM_DEBUG(x...) printk(KERN_INFO x)
|
||||
|
|
|
|||
|
|
@ -2834,6 +2834,9 @@ static void __init prom_find_boot_cpu(void)
|
|||
|
||||
cpu_pkg = call_prom("instance-to-package", 1, 1, prom_cpu);
|
||||
|
||||
if (!PHANDLE_VALID(cpu_pkg))
|
||||
return;
|
||||
|
||||
prom_getprop(cpu_pkg, "reg", &rval, sizeof(rval));
|
||||
prom.cpu = be32_to_cpu(rval);
|
||||
|
||||
|
|
|
|||
|
|
@ -463,6 +463,10 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
|
|||
|
||||
flush_fp_to_thread(target);
|
||||
|
||||
for (i = 0; i < 32 ; i++)
|
||||
buf[i] = target->thread.TS_FPR(i);
|
||||
buf[32] = target->thread.fp_state.fpscr;
|
||||
|
||||
/* copy to local buffer then write that out */
|
||||
i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
|
||||
if (i)
|
||||
|
|
@ -672,6 +676,9 @@ static int vsr_set(struct task_struct *target, const struct user_regset *regset,
|
|||
flush_altivec_to_thread(target);
|
||||
flush_vsx_to_thread(target);
|
||||
|
||||
for (i = 0; i < 32 ; i++)
|
||||
buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
||||
buf, 0, 32 * sizeof(double));
|
||||
if (!ret)
|
||||
|
|
@ -1019,6 +1026,10 @@ static int tm_cfpr_set(struct task_struct *target,
|
|||
flush_fp_to_thread(target);
|
||||
flush_altivec_to_thread(target);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
buf[i] = target->thread.TS_CKFPR(i);
|
||||
buf[32] = target->thread.ckfp_state.fpscr;
|
||||
|
||||
/* copy to local buffer then write that out */
|
||||
i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
|
||||
if (i)
|
||||
|
|
@ -1283,6 +1294,9 @@ static int tm_cvsx_set(struct task_struct *target,
|
|||
flush_altivec_to_thread(target);
|
||||
flush_vsx_to_thread(target);
|
||||
|
||||
for (i = 0; i < 32 ; i++)
|
||||
buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
|
||||
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
||||
buf, 0, 32 * sizeof(double));
|
||||
if (!ret)
|
||||
|
|
|
|||
|
|
@ -747,7 +747,7 @@ static unsigned long __init htab_get_table_size(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_MEMORY_HOTPLUG
|
||||
int create_section_mapping(unsigned long start, unsigned long end)
|
||||
int hash__create_section_mapping(unsigned long start, unsigned long end)
|
||||
{
|
||||
int rc = htab_bolt_mapping(start, end, __pa(start),
|
||||
pgprot_val(PAGE_KERNEL), mmu_linear_psize,
|
||||
|
|
@ -761,7 +761,7 @@ int create_section_mapping(unsigned long start, unsigned long end)
|
|||
return rc;
|
||||
}
|
||||
|
||||
int remove_section_mapping(unsigned long start, unsigned long end)
|
||||
int hash__remove_section_mapping(unsigned long start, unsigned long end)
|
||||
{
|
||||
int rc = htab_remove_mapping(start, end, mmu_linear_psize,
|
||||
mmu_kernel_ssize);
|
||||
|
|
|
|||
|
|
@ -125,11 +125,14 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
|
|||
int hugepd_ok(hugepd_t hpd)
|
||||
{
|
||||
bool is_hugepd;
|
||||
unsigned long hpdval;
|
||||
|
||||
hpdval = hpd_val(hpd);
|
||||
|
||||
/*
|
||||
* We should not find this format in page directory, warn otherwise.
|
||||
*/
|
||||
is_hugepd = (((hpd.pd & 0x3) == 0x0) && ((hpd.pd & HUGEPD_SHIFT_MASK) != 0));
|
||||
is_hugepd = (((hpdval & 0x3) == 0x0) && ((hpdval & HUGEPD_SHIFT_MASK) != 0));
|
||||
WARN(is_hugepd, "Found wrong page directory format\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ static u64 gpage_freearray[MAX_NUMBER_GPAGES];
|
|||
static unsigned nr_gpages;
|
||||
#endif
|
||||
|
||||
#define hugepd_none(hpd) ((hpd).pd == 0)
|
||||
#define hugepd_none(hpd) (hpd_val(hpd) == 0)
|
||||
|
||||
pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
|
||||
{
|
||||
|
|
@ -103,24 +103,24 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
|
|||
for (i = 0; i < num_hugepd; i++, hpdp++) {
|
||||
if (unlikely(!hugepd_none(*hpdp)))
|
||||
break;
|
||||
else
|
||||
else {
|
||||
#ifdef CONFIG_PPC_BOOK3S_64
|
||||
hpdp->pd = __pa(new) |
|
||||
(shift_to_mmu_psize(pshift) << 2);
|
||||
*hpdp = __hugepd(__pa(new) |
|
||||
(shift_to_mmu_psize(pshift) << 2));
|
||||
#elif defined(CONFIG_PPC_8xx)
|
||||
hpdp->pd = __pa(new) |
|
||||
(pshift == PAGE_SHIFT_8M ? _PMD_PAGE_8M :
|
||||
_PMD_PAGE_512K) |
|
||||
_PMD_PRESENT;
|
||||
*hpdp = __hugepd(__pa(new) |
|
||||
(pshift == PAGE_SHIFT_8M ? _PMD_PAGE_8M :
|
||||
_PMD_PAGE_512K) | _PMD_PRESENT);
|
||||
#else
|
||||
/* We use the old format for PPC_FSL_BOOK3E */
|
||||
hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
|
||||
*hpdp = __hugepd(((unsigned long)new & ~PD_HUGE) | pshift);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
/* If we bailed from the for loop early, an error occurred, clean up */
|
||||
if (i < num_hugepd) {
|
||||
for (i = i - 1 ; i >= 0; i--, hpdp--)
|
||||
hpdp->pd = 0;
|
||||
*hpdp = __hugepd(0);
|
||||
kmem_cache_free(cachep, new);
|
||||
}
|
||||
spin_unlock(&mm->page_table_lock);
|
||||
|
|
@ -454,7 +454,7 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
|
|||
return;
|
||||
|
||||
for (i = 0; i < num_hugepd; i++, hpdp++)
|
||||
hpdp->pd = 0;
|
||||
*hpdp = __hugepd(0);
|
||||
|
||||
if (shift >= pdshift)
|
||||
hugepd_free(tlb, hugepte);
|
||||
|
|
@ -810,12 +810,8 @@ static int __init hugetlbpage_init(void)
|
|||
* if we have pdshift and shift value same, we don't
|
||||
* use pgt cache for hugepd.
|
||||
*/
|
||||
if (pdshift > shift) {
|
||||
if (pdshift > shift)
|
||||
pgtable_cache_add(pdshift - shift, NULL);
|
||||
if (!PGT_CACHE(pdshift - shift))
|
||||
panic("hugetlbpage_init(): could not create "
|
||||
"pgtable cache for %d bit pagesize\n", shift);
|
||||
}
|
||||
#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
|
||||
else if (!hugepte_cache) {
|
||||
/*
|
||||
|
|
@ -852,9 +848,6 @@ static int __init hugetlbpage_init(void)
|
|||
else if (mmu_psize_defs[MMU_PAGE_2M].shift)
|
||||
HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_2M].shift;
|
||||
#endif
|
||||
else
|
||||
panic("%s: Unable to set default huge page size\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -78,8 +78,12 @@ void pgtable_cache_add(unsigned shift, void (*ctor)(void *))
|
|||
align = max_t(unsigned long, align, minalign);
|
||||
name = kasprintf(GFP_KERNEL, "pgtable-2^%d", shift);
|
||||
new = kmem_cache_create(name, table_size, align, 0, ctor);
|
||||
if (!new)
|
||||
panic("Could not allocate pgtable cache for order %d", shift);
|
||||
|
||||
kfree(name);
|
||||
pgtable_cache[shift - 1] = new;
|
||||
|
||||
pr_debug("Allocated pgtable cache for order %d\n", shift);
|
||||
}
|
||||
|
||||
|
|
@ -88,7 +92,7 @@ void pgtable_cache_init(void)
|
|||
{
|
||||
pgtable_cache_add(PGD_INDEX_SIZE, pgd_ctor);
|
||||
|
||||
if (PMD_INDEX_SIZE && !PGT_CACHE(PMD_INDEX_SIZE))
|
||||
if (PMD_CACHE_INDEX && !PGT_CACHE(PMD_CACHE_INDEX))
|
||||
pgtable_cache_add(PMD_CACHE_INDEX, pmd_ctor);
|
||||
/*
|
||||
* In all current configs, when the PUD index exists it's the
|
||||
|
|
@ -97,11 +101,4 @@ void pgtable_cache_init(void)
|
|||
*/
|
||||
if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
|
||||
pgtable_cache_add(PUD_INDEX_SIZE, pud_ctor);
|
||||
|
||||
if (!PGT_CACHE(PGD_INDEX_SIZE))
|
||||
panic("Couldn't allocate pgd cache");
|
||||
if (PMD_INDEX_SIZE && !PGT_CACHE(PMD_INDEX_SIZE))
|
||||
panic("Couldn't allocate pmd pgtable caches");
|
||||
if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
|
||||
panic("Couldn't allocate pud pgtable caches");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -126,3 +126,21 @@ void mmu_cleanup_all(void)
|
|||
else if (mmu_hash_ops.hpte_clear_all)
|
||||
mmu_hash_ops.hpte_clear_all();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MEMORY_HOTPLUG
|
||||
int create_section_mapping(unsigned long start, unsigned long end)
|
||||
{
|
||||
if (radix_enabled())
|
||||
return -ENODEV;
|
||||
|
||||
return hash__create_section_mapping(start, end);
|
||||
}
|
||||
|
||||
int remove_section_mapping(unsigned long start, unsigned long end)
|
||||
{
|
||||
if (radix_enabled())
|
||||
return -ENODEV;
|
||||
|
||||
return hash__remove_section_mapping(start, end);
|
||||
}
|
||||
#endif /* CONFIG_MEMORY_HOTPLUG */
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ int radix__map_kernel_page(unsigned long ea, unsigned long pa,
|
|||
if (!pmdp)
|
||||
return -ENOMEM;
|
||||
if (map_page_size == PMD_SIZE) {
|
||||
ptep = (pte_t *)pudp;
|
||||
ptep = pmdp_ptep(pmdp);
|
||||
goto set_the_pte;
|
||||
}
|
||||
ptep = pte_alloc_kernel(pmdp, ea);
|
||||
|
|
@ -90,7 +90,7 @@ int radix__map_kernel_page(unsigned long ea, unsigned long pa,
|
|||
}
|
||||
pmdp = pmd_offset(pudp, ea);
|
||||
if (map_page_size == PMD_SIZE) {
|
||||
ptep = (pte_t *)pudp;
|
||||
ptep = pmdp_ptep(pmdp);
|
||||
goto set_the_pte;
|
||||
}
|
||||
if (!pmd_present(*pmdp)) {
|
||||
|
|
|
|||
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