MIPS: Add code for new system 'paravirt'
For para-virtualized guests running under KVM or other equivalent hypervisor. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
Родитель
90dfdc7ceb
Коммит
18280edafe
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@ -0,0 +1,36 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_tx39_cache 0
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#define cpu_has_counter 1
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#define cpu_has_llsc 1
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/*
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* We Disable LL/SC on non SMP systems as it is faster to disable
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* interrupts for atomic access than a LL/SC.
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*/
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#ifdef CONFIG_SMP
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# define kernel_uses_llsc 1
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#else
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# define kernel_uses_llsc 0
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#endif
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define cpu_dcache_line_size() 128
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#define cpu_icache_line_size() 128
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#define cpu_has_octeon_cache 1
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#define cpu_has_4k_cache 0
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#else
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#define cpu_has_octeon_cache 0
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#define cpu_has_4k_cache 1
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#endif
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#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */
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@ -0,0 +1,19 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#ifndef __ASM_MACH_PARAVIRT_IRQ_H__
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#define __ASM_MACH_PARAVIRT_IRQ_H__
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#define NR_IRQS 64
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#define MIPS_CPU_IRQ_BASE 1
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#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)
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#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
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#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)
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#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */
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@ -0,0 +1,50 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc
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*/
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#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
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#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
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#define CP0_EBASE $15, 1
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.macro kernel_entry_setup
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mfc0 t0, CP0_EBASE
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andi t0, t0, 0x3ff # CPUNum
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beqz t0, 1f
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# CPUs other than zero goto smp_bootstrap
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j smp_bootstrap
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1:
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.endm
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/*
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* Do SMP slave processor setup necessary before we can safely execute
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* C code.
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*/
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.macro smp_slave_setup
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mfc0 t0, CP0_EBASE
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andi t0, t0, 0x3ff # CPUNum
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slti t1, t0, NR_CPUS
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bnez t1, 1f
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2:
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di
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wait
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b 2b # Unknown CPU, loop forever.
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1:
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PTR_LA t1, paravirt_smp_sp
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PTR_SLL t0, PTR_SCALESHIFT
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PTR_ADDU t1, t1, t0
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3:
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PTR_L sp, 0(t1)
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beqz sp, 3b # Spin until told to proceed.
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PTR_LA t1, paravirt_smp_gp
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PTR_ADDU t1, t1, t0
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sync
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PTR_L gp, 0(t1)
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.endm
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#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */
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@ -0,0 +1,25 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com>
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*/
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#ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H
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#define __ASM_MIPS_MACH_PARAVIRT_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */
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@ -1250,17 +1250,13 @@ static void build_r4000_tlb_refill_handler(void)
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unsigned int final_len;
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struct mips_huge_tlb_info htlb_info __maybe_unused;
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enum vmalloc64_mode vmalloc_mode __maybe_unused;
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#ifdef CONFIG_64BIT
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bool is64bit = true;
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#else
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bool is64bit = false;
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#endif
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memset(tlb_handler, 0, sizeof(tlb_handler));
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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if (is64bit && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
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if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
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htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
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scratch_reg);
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vmalloc_mode = refill_scratch;
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@ -0,0 +1,14 @@
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#
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# Makefile for MIPS para-virtualized specific kernel interface routines
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# under Linux.
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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# Copyright (C) 2013 Cavium, Inc.
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#
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obj-y := setup.o serial.o paravirt-irq.o
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obj-$(CONFIG_SMP) += paravirt-smp.o
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@ -0,0 +1,8 @@
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#
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# Generic para-virtualized guest.
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#
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platform-$(CONFIG_MIPS_PARAVIRT) += paravirt/
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cflags-$(CONFIG_MIPS_PARAVIRT) += \
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-I$(srctree)/arch/mips/include/asm/mach-paravirt
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load-$(CONFIG_MIPS_PARAVIRT) = 0xffffffff80010000
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@ -0,0 +1,368 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#include <linux/interrupt.h>
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#include <linux/cpumask.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <asm/io.h>
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#define MBOX_BITS_PER_CPU 2
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static int cpunum_for_cpu(int cpu)
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{
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#ifdef CONFIG_SMP
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return cpu_logical_map(cpu);
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#else
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return get_ebase_cpunum();
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#endif
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}
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struct core_chip_data {
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struct mutex core_irq_mutex;
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bool current_en;
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bool desired_en;
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u8 bit;
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};
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static struct core_chip_data irq_core_chip_data[8];
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static void irq_core_ack(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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unsigned int bit = cd->bit;
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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clear_c0_status(0x100 << bit);
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/* The two user interrupts must be cleared manually. */
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if (bit < 2)
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clear_c0_cause(0x100 << bit);
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}
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static void irq_core_eoi(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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set_c0_status(0x100 << cd->bit);
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}
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static void irq_core_set_enable_local(void *arg)
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{
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struct irq_data *data = arg;
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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unsigned int mask = 0x100 << cd->bit;
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/*
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* Interrupts are already disabled, so these are atomic.
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*/
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if (cd->desired_en)
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set_c0_status(mask);
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else
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clear_c0_status(mask);
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}
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static void irq_core_disable(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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cd->desired_en = false;
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}
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static void irq_core_enable(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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cd->desired_en = true;
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}
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static void irq_core_bus_lock(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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mutex_lock(&cd->core_irq_mutex);
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}
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static void irq_core_bus_sync_unlock(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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if (cd->desired_en != cd->current_en) {
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on_each_cpu(irq_core_set_enable_local, data, 1);
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cd->current_en = cd->desired_en;
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}
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mutex_unlock(&cd->core_irq_mutex);
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}
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static struct irq_chip irq_chip_core = {
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.name = "Core",
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.irq_enable = irq_core_enable,
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.irq_disable = irq_core_disable,
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.irq_ack = irq_core_ack,
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.irq_eoi = irq_core_eoi,
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.irq_bus_lock = irq_core_bus_lock,
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.irq_bus_sync_unlock = irq_core_bus_sync_unlock,
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.irq_cpu_online = irq_core_eoi,
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.irq_cpu_offline = irq_core_ack,
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.flags = IRQCHIP_ONOFFLINE_ENABLED,
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};
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static void __init irq_init_core(void)
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{
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int i;
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int irq;
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struct core_chip_data *cd;
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/* Start with a clean slate */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP0 | CAUSEF_IP1);
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for (i = 0; i < ARRAY_SIZE(irq_core_chip_data); i++) {
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cd = irq_core_chip_data + i;
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cd->current_en = false;
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cd->desired_en = false;
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cd->bit = i;
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mutex_init(&cd->core_irq_mutex);
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irq = MIPS_CPU_IRQ_BASE + i;
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switch (i) {
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case 0: /* SW0 */
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case 1: /* SW1 */
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case 5: /* IP5 */
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case 6: /* IP6 */
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case 7: /* IP7 */
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irq_set_chip_data(irq, cd);
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irq_set_chip_and_handler(irq, &irq_chip_core,
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handle_percpu_irq);
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break;
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default:
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break;
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}
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}
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}
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static void __iomem *mips_irq_chip;
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#define MIPS_IRQ_CHIP_NUM_BITS 0
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#define MIPS_IRQ_CHIP_REGS 8
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static int mips_irq_cpu_stride;
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static int mips_irq_chip_reg_raw;
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static int mips_irq_chip_reg_src;
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static int mips_irq_chip_reg_en;
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static int mips_irq_chip_reg_raw_w1s;
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static int mips_irq_chip_reg_raw_w1c;
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static int mips_irq_chip_reg_en_w1s;
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static int mips_irq_chip_reg_en_w1c;
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static void irq_pci_enable(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
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}
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static void irq_pci_disable(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
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}
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static void irq_pci_ack(struct irq_data *data)
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{
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}
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static void irq_pci_mask(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
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}
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static void irq_pci_unmask(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
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}
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static struct irq_chip irq_chip_pci = {
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.name = "PCI",
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.irq_enable = irq_pci_enable,
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.irq_disable = irq_pci_disable,
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.irq_ack = irq_pci_ack,
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.irq_mask = irq_pci_mask,
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.irq_unmask = irq_pci_unmask,
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};
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static void irq_mbox_all(struct irq_data *data, void __iomem *base)
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{
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int cpu;
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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u32 mask;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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for_each_online_cpu(cpu) {
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unsigned int cpuid = cpunum_for_cpu(cpu);
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mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
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}
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}
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static void irq_mbox_enable(struct irq_data *data)
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{
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irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
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}
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static void irq_mbox_disable(struct irq_data *data)
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{
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irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
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}
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static void irq_mbox_ack(struct irq_data *data)
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{
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u32 mask;
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32));
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}
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void irq_mbox_ipi(int cpu, unsigned int actions)
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{
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unsigned int cpuid = cpunum_for_cpu(cpu);
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u32 mask;
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WARN_ON(actions >= (1 << MBOX_BITS_PER_CPU));
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mask = actions << (cpuid * MBOX_BITS_PER_CPU);
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32));
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}
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static void irq_mbox_cpu_onoffline(struct irq_data *data, void __iomem *base)
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{
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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unsigned int cpuid = get_ebase_cpunum();
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u32 mask;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
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||||
}
|
||||
|
||||
static void irq_mbox_cpu_online(struct irq_data *data)
|
||||
{
|
||||
irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
|
||||
}
|
||||
|
||||
static void irq_mbox_cpu_offline(struct irq_data *data)
|
||||
{
|
||||
irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
|
||||
}
|
||||
|
||||
static struct irq_chip irq_chip_mbox = {
|
||||
.name = "MBOX",
|
||||
.irq_enable = irq_mbox_enable,
|
||||
.irq_disable = irq_mbox_disable,
|
||||
.irq_ack = irq_mbox_ack,
|
||||
.irq_cpu_online = irq_mbox_cpu_online,
|
||||
.irq_cpu_offline = irq_mbox_cpu_offline,
|
||||
.flags = IRQCHIP_ONOFFLINE_ENABLED,
|
||||
};
|
||||
|
||||
static void __init irq_pci_init(void)
|
||||
{
|
||||
int i, stride;
|
||||
u32 num_bits;
|
||||
|
||||
mips_irq_chip = ioremap(0x1e010000, 4096);
|
||||
|
||||
num_bits = __raw_readl(mips_irq_chip + MIPS_IRQ_CHIP_NUM_BITS);
|
||||
stride = 8 * (1 + ((num_bits - 1) / 64));
|
||||
|
||||
|
||||
pr_notice("mips_irq_chip: %u bits, reg stride: %d\n", num_bits, stride);
|
||||
mips_irq_chip_reg_raw = MIPS_IRQ_CHIP_REGS + 0 * stride;
|
||||
mips_irq_chip_reg_raw_w1s = MIPS_IRQ_CHIP_REGS + 1 * stride;
|
||||
mips_irq_chip_reg_raw_w1c = MIPS_IRQ_CHIP_REGS + 2 * stride;
|
||||
mips_irq_chip_reg_src = MIPS_IRQ_CHIP_REGS + 3 * stride;
|
||||
mips_irq_chip_reg_en = MIPS_IRQ_CHIP_REGS + 4 * stride;
|
||||
mips_irq_chip_reg_en_w1s = MIPS_IRQ_CHIP_REGS + 5 * stride;
|
||||
mips_irq_chip_reg_en_w1c = MIPS_IRQ_CHIP_REGS + 6 * stride;
|
||||
mips_irq_cpu_stride = stride * 4;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
irq_set_chip_and_handler(i + MIPS_IRQ_PCIA, &irq_chip_pci, handle_level_irq);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
irq_set_chip_and_handler(i + MIPS_IRQ_MBOX0, &irq_chip_mbox, handle_percpu_irq);
|
||||
|
||||
|
||||
set_c0_status(STATUSF_IP2);
|
||||
}
|
||||
|
||||
static void irq_pci_dispatch(void)
|
||||
{
|
||||
unsigned int cpuid = get_ebase_cpunum();
|
||||
u32 en;
|
||||
|
||||
en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src +
|
||||
(cpuid * mips_irq_cpu_stride));
|
||||
|
||||
if (!en) {
|
||||
en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src + (cpuid * mips_irq_cpu_stride) + sizeof(u32));
|
||||
en = (en >> (2 * cpuid)) & 3;
|
||||
|
||||
if (!en)
|
||||
spurious_interrupt();
|
||||
else
|
||||
do_IRQ(__ffs(en) + MIPS_IRQ_MBOX0); /* MBOX type */
|
||||
} else {
|
||||
do_IRQ(__ffs(en));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
irq_init_core();
|
||||
irq_pci_init();
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
int ip;
|
||||
|
||||
if (unlikely(!pending)) {
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
ip = ffs(pending) - 1 - STATUSB_IP0;
|
||||
if (ip == 2)
|
||||
irq_pci_dispatch();
|
||||
else
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + ip);
|
||||
}
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2013 Cavium, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
/*
|
||||
* Writing the sp releases the CPU, so writes must be ordered, gp
|
||||
* first, then sp.
|
||||
*/
|
||||
unsigned long paravirt_smp_sp[NR_CPUS];
|
||||
unsigned long paravirt_smp_gp[NR_CPUS];
|
||||
|
||||
static int numcpus = 1;
|
||||
|
||||
static int __init set_numcpus(char *str)
|
||||
{
|
||||
int newval;
|
||||
|
||||
if (get_option(&str, &newval)) {
|
||||
if (newval < 1 || newval >= NR_CPUS)
|
||||
goto bad;
|
||||
numcpus = newval;
|
||||
return 0;
|
||||
}
|
||||
bad:
|
||||
return -EINVAL;
|
||||
}
|
||||
early_param("numcpus", set_numcpus);
|
||||
|
||||
|
||||
static void paravirt_smp_setup(void)
|
||||
{
|
||||
int id;
|
||||
unsigned int cpunum = get_ebase_cpunum();
|
||||
|
||||
if (WARN_ON(cpunum >= NR_CPUS))
|
||||
return;
|
||||
|
||||
/* The present CPUs are initially just the boot cpu (CPU 0). */
|
||||
for (id = 0; id < NR_CPUS; id++) {
|
||||
set_cpu_possible(id, id == 0);
|
||||
set_cpu_present(id, id == 0);
|
||||
}
|
||||
__cpu_number_map[cpunum] = 0;
|
||||
__cpu_logical_map[0] = cpunum;
|
||||
|
||||
for (id = 0; id < numcpus; id++) {
|
||||
set_cpu_possible(id, true);
|
||||
set_cpu_present(id, true);
|
||||
__cpu_number_map[id] = id;
|
||||
__cpu_logical_map[id] = id;
|
||||
}
|
||||
}
|
||||
|
||||
void irq_mbox_ipi(int cpu, unsigned int actions);
|
||||
static void paravirt_send_ipi_single(int cpu, unsigned int action)
|
||||
{
|
||||
irq_mbox_ipi(cpu, action);
|
||||
}
|
||||
|
||||
static void paravirt_send_ipi_mask(const struct cpumask *mask, unsigned int action)
|
||||
{
|
||||
unsigned int cpu;
|
||||
|
||||
for_each_cpu_mask(cpu, *mask)
|
||||
paravirt_send_ipi_single(cpu, action);
|
||||
}
|
||||
|
||||
static void paravirt_init_secondary(void)
|
||||
{
|
||||
unsigned int sr;
|
||||
|
||||
sr = set_c0_status(ST0_BEV);
|
||||
write_c0_ebase((u32)ebase);
|
||||
|
||||
sr |= STATUSF_IP2; /* Interrupt controller on IP2 */
|
||||
write_c0_status(sr);
|
||||
|
||||
irq_cpu_online();
|
||||
}
|
||||
|
||||
static void paravirt_smp_finish(void)
|
||||
{
|
||||
/* to generate the first CPU timer interrupt */
|
||||
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
static void paravirt_cpus_done(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void paravirt_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
paravirt_smp_gp[cpu] = (unsigned long)task_thread_info(idle);
|
||||
smp_wmb();
|
||||
paravirt_smp_sp[cpu] = __KSTK_TOS(idle);
|
||||
}
|
||||
|
||||
static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
scheduler_ipi();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t paravirt_function_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void paravirt_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
if (request_irq(MIPS_IRQ_MBOX0, paravirt_reched_interrupt,
|
||||
IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
|
||||
paravirt_reched_interrupt)) {
|
||||
panic("Cannot request_irq for SchedulerIPI");
|
||||
}
|
||||
if (request_irq(MIPS_IRQ_MBOX1, paravirt_function_interrupt,
|
||||
IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
|
||||
paravirt_function_interrupt)) {
|
||||
panic("Cannot request_irq for SMP-Call");
|
||||
}
|
||||
}
|
||||
|
||||
struct plat_smp_ops paravirt_smp_ops = {
|
||||
.send_ipi_single = paravirt_send_ipi_single,
|
||||
.send_ipi_mask = paravirt_send_ipi_mask,
|
||||
.init_secondary = paravirt_init_secondary,
|
||||
.smp_finish = paravirt_smp_finish,
|
||||
.cpus_done = paravirt_cpus_done,
|
||||
.boot_secondary = paravirt_boot_secondary,
|
||||
.smp_setup = paravirt_smp_setup,
|
||||
.prepare_cpus = paravirt_prepare_cpus,
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2013 Cavium, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/virtio_console.h>
|
||||
#include <linux/kvm_para.h>
|
||||
|
||||
/*
|
||||
* Emit one character to the boot console.
|
||||
*/
|
||||
int prom_putchar(char c)
|
||||
{
|
||||
kvm_hypercall3(KVM_HC_MIPS_CONSOLE_OUTPUT, 0 /* port 0 */,
|
||||
(unsigned long)&c, 1 /* len == 1 */);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VIRTIO_CONSOLE
|
||||
static int paravirt_put_chars(u32 vtermno, const char *buf, int count)
|
||||
{
|
||||
kvm_hypercall3(KVM_HC_MIPS_CONSOLE_OUTPUT, vtermno,
|
||||
(unsigned long)buf, count);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static int __init paravirt_cons_init(void)
|
||||
{
|
||||
virtio_cons_early_init(paravirt_put_chars);
|
||||
return 0;
|
||||
}
|
||||
core_initcall(paravirt_cons_init);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2013 Cavium, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/kvm_para.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/smp-ops.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
extern struct plat_smp_ops paravirt_smp_ops;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "MIPS Para-Virtualized Guest";
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
mips_hpt_frequency = kvm_hypercall0(KVM_HC_MIPS_GET_CLOCK_FREQ);
|
||||
|
||||
preset_lpj = mips_hpt_frequency / (2 * HZ);
|
||||
}
|
||||
|
||||
static void pv_machine_halt(void)
|
||||
{
|
||||
kvm_hypercall0(KVM_HC_MIPS_EXIT_VM);
|
||||
}
|
||||
|
||||
/*
|
||||
* Early entry point for arch setup
|
||||
*/
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int i;
|
||||
int argc = fw_arg0;
|
||||
char **argv = (char **)fw_arg1;
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
set_io_port_base(KSEG1ADDR(0x1e000000));
|
||||
#else /* CONFIG_64BIT */
|
||||
set_io_port_base(PHYS_TO_XKSEG_UNCACHED(0x1e000000));
|
||||
#endif
|
||||
|
||||
for (i = 0; i < argc; i++) {
|
||||
strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
|
||||
if (i < argc - 1)
|
||||
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
|
||||
}
|
||||
_machine_halt = pv_machine_halt;
|
||||
register_smp_ops(¶virt_smp_ops);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
/* Do nothing, the "mem=???" parser handles our memory. */
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
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