Merge branch 'for-next/perf-smmu' into for-next/perf
* for-next/perf-smmu: perf/smmuv3: Synthesize IIDR from CoreSight ID registers perf/smmuv3: Add devicetree support dt-bindings: Add Arm SMMUv3 PMCG binding
This commit is contained in:
Will Deacon
Коммит
1879a61f4a
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@ -0,0 +1,70 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm SMMUv3 Performance Monitor Counter Group
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maintainers:
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- Will Deacon <will@kernel.org>
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- Robin Murphy <robin.murphy@arm.com>
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description: |
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An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
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They are standalone performance monitoring units that support both
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architected and IMPLEMENTATION DEFINED event counters.
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properties:
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$nodename:
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pattern: "^pmu@[0-9a-f]*"
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compatible:
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oneOf:
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- items:
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- const: arm,mmu-600-pmcg
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- const: arm,smmu-v3-pmcg
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- const: arm,smmu-v3-pmcg
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reg:
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items:
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- description: Register page 0
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- description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
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minItems: 1
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interrupts:
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maxItems: 1
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msi-parent: true
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required:
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- compatible
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- reg
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anyOf:
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- required:
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- interrupts
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- required:
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- msi-parent
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pmu@2b420000 {
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compatible = "arm,smmu-v3-pmcg";
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reg = <0x2b420000 0x1000>,
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<0x2b430000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
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msi-parent = <&its 0xff0000>;
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};
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pmu@2b440000 {
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compatible = "arm,smmu-v3-pmcg";
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reg = <0x2b440000 0x1000>,
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<0x2b450000 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
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msi-parent = <&its 0xff0000>;
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};
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@ -47,6 +47,7 @@
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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@ -75,6 +76,10 @@
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#define SMMU_PMCG_CR 0xE04
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#define SMMU_PMCG_CR_ENABLE BIT(0)
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#define SMMU_PMCG_IIDR 0xE08
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#define SMMU_PMCG_IIDR_PRODUCTID GENMASK(31, 20)
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#define SMMU_PMCG_IIDR_VARIANT GENMASK(19, 16)
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#define SMMU_PMCG_IIDR_REVISION GENMASK(15, 12)
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#define SMMU_PMCG_IIDR_IMPLEMENTER GENMASK(11, 0)
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#define SMMU_PMCG_CEID0 0xE20
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#define SMMU_PMCG_CEID1 0xE28
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#define SMMU_PMCG_IRQ_CTRL 0xE50
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@ -83,6 +88,20 @@
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#define SMMU_PMCG_IRQ_CFG1 0xE60
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#define SMMU_PMCG_IRQ_CFG2 0xE64
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/* IMP-DEF ID registers */
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#define SMMU_PMCG_PIDR0 0xFE0
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#define SMMU_PMCG_PIDR0_PART_0 GENMASK(7, 0)
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#define SMMU_PMCG_PIDR1 0xFE4
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#define SMMU_PMCG_PIDR1_DES_0 GENMASK(7, 4)
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#define SMMU_PMCG_PIDR1_PART_1 GENMASK(3, 0)
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#define SMMU_PMCG_PIDR2 0xFE8
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#define SMMU_PMCG_PIDR2_REVISION GENMASK(7, 4)
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#define SMMU_PMCG_PIDR2_DES_1 GENMASK(2, 0)
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#define SMMU_PMCG_PIDR3 0xFEC
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#define SMMU_PMCG_PIDR3_REVAND GENMASK(7, 4)
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#define SMMU_PMCG_PIDR4 0xFD0
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#define SMMU_PMCG_PIDR4_DES_2 GENMASK(3, 0)
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/* MSI config fields */
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#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
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#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1
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@ -754,6 +773,41 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
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dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
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}
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static bool smmu_pmu_coresight_id_regs(struct smmu_pmu *smmu_pmu)
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{
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return of_device_is_compatible(smmu_pmu->dev->of_node,
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"arm,mmu-600-pmcg");
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}
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static void smmu_pmu_get_iidr(struct smmu_pmu *smmu_pmu)
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{
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u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
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if (!iidr && smmu_pmu_coresight_id_regs(smmu_pmu)) {
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u32 pidr0 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR0);
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u32 pidr1 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR1);
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u32 pidr2 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR2);
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u32 pidr3 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR3);
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u32 pidr4 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR4);
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u32 productid = FIELD_GET(SMMU_PMCG_PIDR0_PART_0, pidr0) |
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(FIELD_GET(SMMU_PMCG_PIDR1_PART_1, pidr1) << 8);
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u32 variant = FIELD_GET(SMMU_PMCG_PIDR2_REVISION, pidr2);
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u32 revision = FIELD_GET(SMMU_PMCG_PIDR3_REVAND, pidr3);
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u32 implementer =
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FIELD_GET(SMMU_PMCG_PIDR1_DES_0, pidr1) |
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(FIELD_GET(SMMU_PMCG_PIDR2_DES_1, pidr2) << 4) |
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(FIELD_GET(SMMU_PMCG_PIDR4_DES_2, pidr4) << 8);
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iidr = FIELD_PREP(SMMU_PMCG_IIDR_PRODUCTID, productid) |
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FIELD_PREP(SMMU_PMCG_IIDR_VARIANT, variant) |
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FIELD_PREP(SMMU_PMCG_IIDR_REVISION, revision) |
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FIELD_PREP(SMMU_PMCG_IIDR_IMPLEMENTER, implementer);
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}
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smmu_pmu->iidr = iidr;
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}
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static int smmu_pmu_probe(struct platform_device *pdev)
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{
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struct smmu_pmu *smmu_pmu;
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@ -825,7 +879,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
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return err;
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}
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smmu_pmu->iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR);
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smmu_pmu_get_iidr(smmu_pmu);
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name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
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(res_0->start) >> SMMU_PMCG_PA_SHIFT);
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@ -834,7 +888,8 @@ static int smmu_pmu_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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smmu_pmu_get_acpi_options(smmu_pmu);
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if (!dev->of_node)
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smmu_pmu_get_acpi_options(smmu_pmu);
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/* Pick one CPU to be the preferred one to use */
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smmu_pmu->on_cpu = raw_smp_processor_id();
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@ -884,9 +939,16 @@ static void smmu_pmu_shutdown(struct platform_device *pdev)
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smmu_pmu_disable(&smmu_pmu->pmu);
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}
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static const struct of_device_id smmu_pmu_of_match[] = {
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{ .compatible = "arm,smmu-v3-pmcg" },
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{}
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};
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MODULE_DEVICE_TABLE(of, smmu_pmu_of_match);
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static struct platform_driver smmu_pmu_driver = {
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.driver = {
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.name = "arm-smmu-v3-pmcg",
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.of_match_table = of_match_ptr(smmu_pmu_of_match),
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.suppress_bind_attrs = true,
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},
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.probe = smmu_pmu_probe,
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