powerpc: Remove 64-bit cpu support from ppc32.
These days there is no good reason to run a ppc32 kernel on a 64-bit cpu, rather than a ppc64 kernel, so remove the config option and a bunch of code (and ifdefs) from head.S. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras
Родитель
7c8c6b9776
Коммит
187a00679a
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@ -109,10 +109,6 @@ config 40x
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config 44x
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bool "AMCC 44x"
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config PPC64BRIDGE
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select PPC_FPU
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bool "POWER3, POWER4 and PPC970 (G5)"
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config 8xx
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bool "Freescale 8xx"
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@ -125,7 +121,7 @@ endchoice
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config POWER4_ONLY
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bool "Optimize for POWER4"
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depends on PPC64 || PPC64BRIDGE
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depends on PPC64
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default n
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---help---
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Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
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@ -134,16 +130,16 @@ config POWER4_ONLY
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config POWER3
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bool
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depends on PPC64 || PPC64BRIDGE
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depends on PPC64
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default y if !POWER4_ONLY
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config POWER4
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depends on PPC64 || PPC64BRIDGE
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depends on PPC64
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def_bool y
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config PPC_FPU
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depends on PPC32
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def_bool y
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bool
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default y if PPC64
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config BOOKE
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bool
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@ -317,7 +313,7 @@ config PPC_BPA
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config PPC_OF
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bool
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depends on PPC_MULTIPLATFORM || PPC_ISERIES
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depends on PPC_MULTIPLATFORM # for now
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default y
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config XICS
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@ -37,19 +37,6 @@
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#include <asm/amigappc.h>
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#endif
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#ifdef CONFIG_PPC64BRIDGE
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#define LOAD_BAT(n, reg, RA, RB) \
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ld RA,(n*32)+0(reg); \
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ld RB,(n*32)+8(reg); \
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mtspr SPRN_IBAT##n##U,RA; \
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mtspr SPRN_IBAT##n##L,RB; \
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ld RA,(n*32)+16(reg); \
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ld RB,(n*32)+24(reg); \
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mtspr SPRN_DBAT##n##U,RA; \
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mtspr SPRN_DBAT##n##L,RB; \
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#else /* CONFIG_PPC64BRIDGE */
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/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
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#define LOAD_BAT(n, reg, RA, RB) \
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/* see the comment for clear_bats() -- Cort */ \
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@ -66,7 +53,6 @@
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mtspr SPRN_DBAT##n##U,RA; \
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mtspr SPRN_DBAT##n##L,RB; \
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1:
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#endif /* CONFIG_PPC64BRIDGE */
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.text
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.stabs "arch/ppc/kernel/",N_SO,0,0,0f
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@ -150,14 +136,6 @@ __start:
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*/
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bl early_init
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/*
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* On POWER4, we first need to tweak some CPU configuration registers
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* like real mode cache inhibit or exception base
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*/
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#ifdef CONFIG_POWER4
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bl __970_cpu_preinit
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#endif /* CONFIG_POWER4 */
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#ifdef CONFIG_APUS
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/* On APUS the __va/__pa constants need to be set to the correct
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* values before continuing.
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@ -171,7 +149,6 @@ __start:
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*/
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bl mmu_off
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__after_mmu_off:
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#ifndef CONFIG_POWER4
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bl clear_bats
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bl flush_tlbs
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@ -179,10 +156,6 @@ __after_mmu_off:
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#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
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bl setup_disp_bat
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#endif
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#else /* CONFIG_POWER4 */
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bl reloc_offset
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bl initial_mm_power4
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#endif /* CONFIG_POWER4 */
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/*
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* Call setup_cpu for CPU 0 and initialize 6xx Idle
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@ -194,10 +167,6 @@ __after_mmu_off:
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bl reloc_offset
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bl init_idle_6xx
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#endif /* CONFIG_6xx */
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#ifdef CONFIG_POWER4
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bl reloc_offset
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bl init_idle_power4
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#endif /* CONFIG_POWER4 */
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#ifndef CONFIG_APUS
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@ -397,13 +366,8 @@ i##n: \
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/* Data access exception. */
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. = 0x300
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#ifdef CONFIG_PPC64BRIDGE
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b DataAccess
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DataAccessCont:
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#else
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DataAccess:
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EXCEPTION_PROLOG
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#endif /* CONFIG_PPC64BRIDGE */
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mfspr r10,SPRN_DSISR
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andis. r0,r10,0xa470 /* weird error? */
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bne 1f /* if not, try to put a PTE */
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@ -415,21 +379,11 @@ DataAccess:
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mfspr r4,SPRN_DAR
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EXC_XFER_EE_LITE(0x300, handle_page_fault)
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#ifdef CONFIG_PPC64BRIDGE
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/* SLB fault on data access. */
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. = 0x380
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b DataSegment
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#endif /* CONFIG_PPC64BRIDGE */
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/* Instruction access exception. */
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. = 0x400
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#ifdef CONFIG_PPC64BRIDGE
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b InstructionAccess
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InstructionAccessCont:
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#else
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InstructionAccess:
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EXCEPTION_PROLOG
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#endif /* CONFIG_PPC64BRIDGE */
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andis. r0,r9,0x4000 /* no pte found? */
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beq 1f /* if so, try to put a PTE */
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li r3,0 /* into the hash table */
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@ -439,12 +393,6 @@ InstructionAccess:
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mr r5,r9
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EXC_XFER_EE_LITE(0x400, handle_page_fault)
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#ifdef CONFIG_PPC64BRIDGE
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/* SLB fault on instruction access. */
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. = 0x480
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b InstructionSegment
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#endif /* CONFIG_PPC64BRIDGE */
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/* External interrupt */
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EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
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@ -709,15 +657,9 @@ DataStoreTLBMiss:
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EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
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EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
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EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
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#ifdef CONFIG_POWER4
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EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
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EXCEPTION(0x1700, Trap_17, altivec_assist_exception, EXC_XFER_EE)
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EXCEPTION(0x1800, Trap_18, TAUException, EXC_XFER_STD)
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#else /* !CONFIG_POWER4 */
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EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
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EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
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EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
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#endif /* CONFIG_POWER4 */
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EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
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EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
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EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
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@ -754,28 +696,6 @@ AltiVecUnavailable:
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#endif /* CONFIG_ALTIVEC */
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EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
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#ifdef CONFIG_PPC64BRIDGE
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DataAccess:
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EXCEPTION_PROLOG
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b DataAccessCont
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InstructionAccess:
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EXCEPTION_PROLOG
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b InstructionAccessCont
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DataSegment:
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EXCEPTION_PROLOG
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addi r3,r1,STACK_FRAME_OVERHEAD
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mfspr r4,SPRN_DAR
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stw r4,_DAR(r11)
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EXC_XFER_STD(0x380, unknown_exception)
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InstructionSegment:
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EXCEPTION_PROLOG
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_STD(0x480, unknown_exception)
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#endif /* CONFIG_PPC64BRIDGE */
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#ifdef CONFIG_ALTIVEC
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/* Note that the AltiVec support is closely modeled after the FP
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* support. Changes to one are likely to be applicable to the
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@ -1048,13 +968,6 @@ __secondary_start_pmac_0:
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.globl __secondary_start
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__secondary_start:
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#ifdef CONFIG_PPC64BRIDGE
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mfmsr r0
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clrldi r0,r0,1 /* make sure it's in 32-bit mode */
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SYNC
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MTMSRD(r0)
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isync
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#endif
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/* Copy some CPU settings from CPU 0 */
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bl __restore_cpu_setup
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@ -1065,10 +978,6 @@ __secondary_start:
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lis r3,-KERNELBASE@h
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bl init_idle_6xx
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#endif /* CONFIG_6xx */
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#ifdef CONFIG_POWER4
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lis r3,-KERNELBASE@h
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bl init_idle_power4
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#endif /* CONFIG_POWER4 */
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/* get current_thread_info and current */
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lis r1,secondary_ti@ha
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@ -1109,12 +1018,12 @@ __secondary_start:
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* Those generic dummy functions are kept for CPUs not
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* included in CONFIG_6xx
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*/
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#if !defined(CONFIG_6xx) && !defined(CONFIG_POWER4)
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#if !defined(CONFIG_6xx)
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_GLOBAL(__save_cpu_setup)
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blr
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_GLOBAL(__restore_cpu_setup)
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blr
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#endif /* !defined(CONFIG_6xx) && !defined(CONFIG_POWER4) */
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#endif /* !defined(CONFIG_6xx) */
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/*
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@ -1132,11 +1041,6 @@ load_up_mmu:
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tophys(r6,r6)
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lwz r6,_SDR1@l(r6)
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mtspr SPRN_SDR1,r6
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#ifdef CONFIG_PPC64BRIDGE
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/* clear the ASR so we only use the pseudo-segment registers. */
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li r6,0
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mtasr r6
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#endif /* CONFIG_PPC64BRIDGE */
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li r0,16 /* load up segment register values */
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mtctr r0 /* for context 0 */
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lis r3,0x2000 /* Ku = 1, VSID = 0 */
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@ -1145,7 +1049,7 @@ load_up_mmu:
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addi r3,r3,0x111 /* increment VSID */
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addis r4,r4,0x1000 /* address of next segment */
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bdnz 3b
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#ifndef CONFIG_POWER4
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/* Load the BAT registers with the values set up by MMU_init.
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MMU_init takes care of whether we're on a 601 or not. */
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mfpvr r3
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@ -1158,7 +1062,7 @@ load_up_mmu:
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LOAD_BAT(1,r3,r4,r5)
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LOAD_BAT(2,r3,r4,r5)
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LOAD_BAT(3,r3,r4,r5)
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#endif /* CONFIG_POWER4 */
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blr
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/*
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@ -1183,7 +1087,7 @@ start_here:
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li r0,0
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stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
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/*
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* Do early bootinfo parsing, platform-specific initialization,
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* Do early platform-specific initialization,
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* and set up the MMU.
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*/
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mr r3,r31
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@ -1266,9 +1170,6 @@ _GLOBAL(set_context)
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li r4,0
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isync
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3:
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#ifdef CONFIG_PPC64BRIDGE
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slbie r4
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#endif /* CONFIG_PPC64BRIDGE */
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mtsrin r3,r4
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addi r3,r3,0x111 /* next VSID */
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rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
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@ -1355,7 +1256,6 @@ mmu_off:
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sync
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RFI
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#ifndef CONFIG_POWER4
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/*
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* Use the first pair of BAT registers to map the 1st 16MB
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* of RAM to KERNELBASE. From this point on we can't safely
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@ -1363,7 +1263,6 @@ mmu_off:
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*/
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initial_bats:
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lis r11,KERNELBASE@h
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#ifndef CONFIG_PPC64BRIDGE
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mfspr r9,SPRN_PVR
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rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
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cmpwi 0,r9,1
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@ -1378,7 +1277,6 @@ initial_bats:
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mtspr SPRN_IBAT1L,r10
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isync
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blr
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#endif /* CONFIG_PPC64BRIDGE */
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4: tophys(r8,r11)
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#ifdef CONFIG_SMP
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@ -1392,11 +1290,6 @@ initial_bats:
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ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
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#endif /* CONFIG_APUS */
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#ifdef CONFIG_PPC64BRIDGE
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/* clear out the high 32 bits in the BAT */
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clrldi r11,r11,32
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clrldi r8,r8,32
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#endif /* CONFIG_PPC64BRIDGE */
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mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
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mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
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mtspr SPRN_IBAT0L,r8
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@ -1429,37 +1322,6 @@ setup_disp_bat:
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#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
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#else /* CONFIG_POWER4 */
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/*
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* Load up the SDR1 and segment register values now
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* since we don't have the BATs.
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* Also make sure we are running in 32-bit mode.
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*/
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initial_mm_power4:
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addis r14,r3,_SDR1@ha /* get the value from _SDR1 */
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lwz r14,_SDR1@l(r14) /* assume hash table below 4GB */
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mtspr SPRN_SDR1,r14
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slbia
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lis r4,0x2000 /* set pseudo-segment reg 12 */
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ori r5,r4,0x0ccc
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mtsr 12,r5
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#if 0
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ori r5,r4,0x0888 /* set pseudo-segment reg 8 */
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mtsr 8,r5 /* (for access to serial port) */
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#endif
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#ifdef CONFIG_BOOTX_TEXT
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ori r5,r4,0x0999 /* set pseudo-segment reg 9 */
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mtsr 9,r5 /* (for access to screen) */
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#endif
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mfmsr r0
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clrldi r0,r0,1
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sync
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mtmsr r0
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isync
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blr
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#endif /* CONFIG_POWER4 */
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#ifdef CONFIG_8260
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/* Jump into the system reset for the rom.
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