[PATCH] USB: EHCI updates split init/reinit logic for resume
Moving the PCI-specific parts of the EHCI driver into their own file created a few issues ... notably on resume paths which (like swsusp) require re-initializing the controller. This patch: - Splits the EHCI startup code into run-once HCD setup code and separate "init the hardware" reinit code. (That reinit code is a superset of the "early usb handoff" code.) - Then it makes the PCI init code run both, and the resume code only run the reinit code. - It also removes needless pci wrappers around EHCI start/stop methods. - Removes a byteswap issue that would be seen on big-endian hardware. The HCD glue still doesn't actually provide a good way to do all this run-one init stuff in one place though. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
David Brownell
Linus Torvalds
Родитель
abcc944806
Коммит
188075211c
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@ -411,50 +411,39 @@ static void ehci_stop (struct usb_hcd *hcd)
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dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
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}
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static int ehci_run (struct usb_hcd *hcd)
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/* one-time init, only for memory state */
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static int ehci_init(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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u32 temp;
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int retval;
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u32 hcc_params;
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int first;
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/* skip some things on restart paths */
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first = (ehci->watchdog.data == 0);
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if (first) {
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init_timer (&ehci->watchdog);
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ehci->watchdog.function = ehci_watchdog;
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ehci->watchdog.data = (unsigned long) ehci;
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}
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spin_lock_init(&ehci->lock);
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init_timer(&ehci->watchdog);
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ehci->watchdog.function = ehci_watchdog;
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ehci->watchdog.data = (unsigned long) ehci;
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/*
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* hw default: 1K periodic list heads, one per frame.
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* periodic_size can shrink by USBCMD update if hcc_params allows.
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*/
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ehci->periodic_size = DEFAULT_I_TDPS;
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if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
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if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
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return retval;
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/* controllers may cache some of the periodic schedule ... */
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hcc_params = readl (&ehci->caps->hcc_params);
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if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
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hcc_params = readl(&ehci->caps->hcc_params);
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if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
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ehci->i_thresh = 8;
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else // N microframes cached
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ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
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ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
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ehci->reclaim = NULL;
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ehci->reclaim_ready = 0;
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ehci->next_uframe = -1;
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/* controller state: unknown --> reset */
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/* EHCI spec section 4.1 */
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if ((retval = ehci_reset (ehci)) != 0) {
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ehci_mem_cleanup (ehci);
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return retval;
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}
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writel (ehci->periodic_dma, &ehci->regs->frame_list);
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/*
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* dedicate a qh for the async ring head, since we couldn't unlink
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* a 'real' qh without stopping the async schedule [4.8]. use it
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@ -462,37 +451,13 @@ static int ehci_run (struct usb_hcd *hcd)
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* its dummy is used in hw_alt_next of many tds, to prevent the qh
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* from automatically advancing to the next td after short reads.
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*/
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if (first) {
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ehci->async->qh_next.qh = NULL;
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ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
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ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
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ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
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ehci->async->hw_qtd_next = EHCI_LIST_END;
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ehci->async->qh_state = QH_STATE_LINKED;
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ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
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}
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writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
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/*
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* hcc_params controls whether ehci->regs->segment must (!!!)
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* be used; it constrains QH/ITD/SITD and QTD locations.
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* pci_pool consistent memory always uses segment zero.
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* streaming mappings for I/O buffers, like pci_map_single(),
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* can return segments above 4GB, if the device allows.
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*
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* NOTE: the dma mask is visible through dma_supported(), so
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* drivers can pass this info along ... like NETIF_F_HIGHDMA,
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* Scsi_Host.highmem_io, and so forth. It's readonly to all
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* host side drivers though.
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*/
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if (HCC_64BIT_ADDR (hcc_params)) {
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writel (0, &ehci->regs->segment);
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#if 0
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// this is deeply broken on almost all architectures
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if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK))
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ehci_info (ehci, "enabled 64bit DMA\n");
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#endif
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}
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ehci->async->qh_next.qh = NULL;
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ehci->async->hw_next = QH_NEXT(ehci->async->qh_dma);
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ehci->async->hw_info1 = cpu_to_le32(QH_HEAD);
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ehci->async->hw_token = cpu_to_le32(QTD_STS_HALT);
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ehci->async->hw_qtd_next = EHCI_LIST_END;
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ehci->async->qh_state = QH_STATE_LINKED;
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ehci->async->hw_alt_next = QTD_NEXT(ehci->async->dummy->qtd_dma);
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/* clear interrupt enables, set irq latency */
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if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
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@ -507,13 +472,13 @@ static int ehci_run (struct usb_hcd *hcd)
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* make problems: throughput reduction (!), data errors...
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*/
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if (park) {
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park = min (park, (unsigned) 3);
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park = min(park, (unsigned) 3);
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temp |= CMD_PARK;
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temp |= park << 8;
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}
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ehci_info (ehci, "park %d\n", park);
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ehci_dbg(ehci, "park %d\n", park);
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}
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if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
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if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
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/* periodic schedule size can be smaller than default */
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temp &= ~(3 << 2);
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temp |= (EHCI_TUNE_FLS << 2);
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@ -521,16 +486,63 @@ static int ehci_run (struct usb_hcd *hcd)
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case 0: ehci->periodic_size = 1024; break;
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case 1: ehci->periodic_size = 512; break;
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case 2: ehci->periodic_size = 256; break;
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default: BUG ();
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default: BUG();
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}
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}
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ehci->command = temp;
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ehci->reboot_notifier.notifier_call = ehci_reboot;
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register_reboot_notifier(&ehci->reboot_notifier);
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return 0;
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}
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/* start HC running; it's halted, ehci_init() has been run (once) */
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static int ehci_run (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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int retval;
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u32 temp;
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u32 hcc_params;
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/* EHCI spec section 4.1 */
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if ((retval = ehci_reset(ehci)) != 0) {
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unregister_reboot_notifier(&ehci->reboot_notifier);
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ehci_mem_cleanup(ehci);
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return retval;
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}
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writel(ehci->periodic_dma, &ehci->regs->frame_list);
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writel((u32)ehci->async->qh_dma, &ehci->regs->async_next);
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/*
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* hcc_params controls whether ehci->regs->segment must (!!!)
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* be used; it constrains QH/ITD/SITD and QTD locations.
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* pci_pool consistent memory always uses segment zero.
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* streaming mappings for I/O buffers, like pci_map_single(),
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* can return segments above 4GB, if the device allows.
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*
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* NOTE: the dma mask is visible through dma_supported(), so
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* drivers can pass this info along ... like NETIF_F_HIGHDMA,
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* Scsi_Host.highmem_io, and so forth. It's readonly to all
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* host side drivers though.
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*/
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hcc_params = readl(&ehci->caps->hcc_params);
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if (HCC_64BIT_ADDR(hcc_params)) {
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writel(0, &ehci->regs->segment);
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#if 0
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// this is deeply broken on almost all architectures
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if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
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ehci_info(ehci, "enabled 64bit DMA\n");
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#endif
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}
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// Philips, Intel, and maybe others need CMD_RUN before the
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// root hub will detect new devices (why?); NEC doesn't
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temp |= CMD_RUN;
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writel (temp, &ehci->regs->command);
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dbg_cmd (ehci, "init", temp);
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/* set async sleep time = 10 us ... ? */
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ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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ehci->command |= CMD_RUN;
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writel (ehci->command, &ehci->regs->command);
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dbg_cmd (ehci, "init", ehci->command);
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/*
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* Start, enabling full USB 2.0 functionality ... usb 1.1 devices
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@ -538,26 +550,23 @@ static int ehci_run (struct usb_hcd *hcd)
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* involved with the root hub. (Except where one is integrated,
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* and there's no companion controller unless maybe for USB OTG.)
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*/
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if (first) {
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ehci->reboot_notifier.notifier_call = ehci_reboot;
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register_reboot_notifier (&ehci->reboot_notifier);
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}
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hcd->state = HC_STATE_RUNNING;
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writel (FLAG_CF, &ehci->regs->configured_flag);
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readl (&ehci->regs->command); /* unblock posted write */
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readl (&ehci->regs->command); /* unblock posted writes */
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temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
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ehci_info (ehci,
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"USB %x.%x %s, EHCI %x.%02x, driver %s\n",
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"USB %x.%x started, EHCI %x.%02x, driver %s\n",
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((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
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first ? "initialized" : "restarted",
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temp >> 8, temp & 0xff, DRIVER_VERSION);
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writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
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if (first)
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create_debug_files (ehci);
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/* GRR this is run-once init(), being done every time the HC starts.
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* So long as they're part of class devices, we can't do it init()
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* since the class device isn't created that early.
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*/
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create_debug_files(ehci);
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return 0;
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}
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@ -58,15 +58,76 @@ static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
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return 0;
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}
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/* called by khubd or root hub init threads */
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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{
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u32 temp;
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int retval;
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unsigned count = 256/4;
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = ehci_to_hcd(ehci)->regs + temp;
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temp = readl(&ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
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/* EHCI 0.96 and later may have "extended capabilities" */
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while (temp && count--) {
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u32 cap;
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pci_read_config_dword(pdev, temp, &cap);
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ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff */
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if (bios_handoff(ehci, temp, cap) != 0)
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return -EOPNOTSUPP;
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break;
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case 0: /* illegal reserved capability */
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ehci_dbg(ehci, "illegal capability!\n");
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cap = 0;
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/* FALLTHROUGH */
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default: /* unknown */
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break;
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}
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temp = (cap >> 8) & 0xff;
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}
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if (!count) {
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ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
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return -EIO;
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}
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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retval = pci_set_mwi(pdev);
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if (!retval)
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ehci_dbg(ehci, "MWI active\n");
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ehci_port_power(ehci, 0);
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return 0;
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}
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/* called by khubd or root hub (re)init threads; leaves HC in halt state */
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static int ehci_pci_reset(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u32 temp;
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unsigned count = 256/4;
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spin_lock_init (&ehci->lock);
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int retval;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
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@ -76,6 +137,10 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = readl(&ehci->caps->hcs_params);
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retval = ehci_halt(ehci);
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if (retval)
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return retval;
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/* NOTE: only the parts below this line are PCI-specific */
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switch (pdev->vendor) {
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@ -111,57 +176,9 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
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break;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = readl(&ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
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/* EHCI 0.96 and later may have "extended capabilities" */
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while (temp && count--) {
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u32 cap;
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pci_read_config_dword(to_pci_dev(hcd->self.controller),
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temp, &cap);
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ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff */
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if (bios_handoff(ehci, temp, cap) != 0)
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return -EOPNOTSUPP;
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break;
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case 0: /* illegal reserved capability */
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ehci_warn(ehci, "illegal capability!\n");
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cap = 0;
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/* FALLTHROUGH */
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default: /* unknown */
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break;
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}
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temp = (cap >> 8) & 0xff;
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}
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if (!count) {
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ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
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return -EIO;
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}
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if (ehci_is_TDI(ehci))
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ehci_reset(ehci);
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ehci_port_power(ehci, 0);
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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@ -184,39 +201,15 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
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}
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}
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/* force HC to halt state */
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return ehci_halt(ehci);
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}
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static int ehci_pci_start(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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int result = 0;
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struct pci_dev *pdev;
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u16 port_wake;
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pdev = to_pci_dev(hcd->self.controller);
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* port wake capability, reported by boot firmware */
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pci_read_config_word(pdev, 0x62, &port_wake);
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hcd->can_wakeup = (port_wake & 1) != 0;
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/* REVISIT: per-port wake capability (PCI 0x62) currently unused */
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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result = pci_set_mwi(pdev);
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if (!result)
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ehci_dbg(ehci, "MWI active\n");
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retval = ehci_pci_reinit(ehci, pdev);
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|
||||
return ehci_run(hcd);
|
||||
}
|
||||
|
||||
/* always called by thread; normally rmmod */
|
||||
|
||||
static void ehci_pci_stop(struct usb_hcd *hcd)
|
||||
{
|
||||
ehci_stop(hcd);
|
||||
/* finish init */
|
||||
return ehci_init(hcd);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
|
@ -250,6 +243,7 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
|
|||
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
||||
unsigned port;
|
||||
struct usb_device *root = hcd->self.root_hub;
|
||||
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
|
||||
int retval = -EINVAL;
|
||||
|
||||
// maybe restore FLADJ
|
||||
|
|
@ -258,7 +252,7 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
|
|||
msleep(100);
|
||||
|
||||
/* If CF is clear, we lost PCI Vaux power and need to restart. */
|
||||
if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
|
||||
if (readl(&ehci->regs->configured_flag) != FLAG_CF)
|
||||
goto restart;
|
||||
|
||||
/* If any port is suspended (or owned by the companion),
|
||||
|
|
@ -292,7 +286,7 @@ restart:
|
|||
*/
|
||||
(void) ehci_halt(ehci);
|
||||
(void) ehci_reset(ehci);
|
||||
(void) ehci_pci_reset(hcd);
|
||||
(void) ehci_pci_reinit(ehci, pdev);
|
||||
|
||||
/* emptying the schedule aborts any urbs */
|
||||
spin_lock_irq(&ehci->lock);
|
||||
|
|
@ -304,9 +298,7 @@ restart:
|
|||
/* restart; khubd will disconnect devices */
|
||||
retval = ehci_run(hcd);
|
||||
|
||||
/* here we "know" root ports should always stay powered;
|
||||
* but some controllers may lose all power.
|
||||
*/
|
||||
/* here we "know" root ports should always stay powered */
|
||||
ehci_port_power(ehci, 1);
|
||||
|
||||
return retval;
|
||||
|
|
@ -328,12 +320,12 @@ static const struct hc_driver ehci_pci_hc_driver = {
|
|||
* basic lifecycle operations
|
||||
*/
|
||||
.reset = ehci_pci_reset,
|
||||
.start = ehci_pci_start,
|
||||
.start = ehci_run,
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = ehci_pci_suspend,
|
||||
.resume = ehci_pci_resume,
|
||||
#endif
|
||||
.stop = ehci_pci_stop,
|
||||
.stop = ehci_stop,
|
||||
|
||||
/*
|
||||
* managing i/o requests and associated device resources
|
||||
|
|
|
|||
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