iwl3945: sync tx queue data structure with iwlagn
We are now using the iwl_tx_queue for iwl3945. To reach that goal, we included the 3945 specific tfd frame structure to iwl_tx_queue. This has no effect on the current iwlagn code. Signed-off-by: Samuel Ortiz <samuel.ortiz@intel.com> Signed-off-by: Abhijeet Kolekar <abhijeet.kolekar@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Samuel Ortiz
John W. Linville
Родитель
42427b4e43
Коммит
188cf6c73a
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@ -240,7 +240,6 @@ struct iwl3945_eeprom {
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#define TFD_QUEUE_MIN 0
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#define TFD_QUEUE_MAX 6
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#define TFD_QUEUE_SIZE_MAX (256)
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#define IWL_NUM_SCAN_RATES (2)
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@ -262,9 +261,6 @@ struct iwl3945_eeprom {
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#define TFD_CTL_PAD_SET(n) (n << 28)
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#define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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/*
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* RX related structures and functions
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*/
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@ -306,7 +306,7 @@ int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
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static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
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int txq_id, int index)
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{
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struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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struct iwl_tx_info *tx_info;
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@ -337,7 +337,7 @@ static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
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u16 sequence = le16_to_cpu(pkt->hdr.sequence);
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int txq_id = SEQ_TO_QUEUE(sequence);
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int index = SEQ_TO_INDEX(sequence);
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struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct ieee80211_tx_info *info;
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struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
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u32 status = le32_to_cpu(tx_resp->status);
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@ -756,9 +756,9 @@ int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
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*
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* Does NOT advance any indexes
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*/
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int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
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int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds[0];
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struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds39[0];
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struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
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struct pci_dev *dev = priv->pci_dev;
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int i;
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@ -1061,7 +1061,7 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
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for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
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slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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rc = iwl3945_tx_queue_init(priv, &priv->txq39[txq_id], slots_num,
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rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
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txq_id);
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if (rc) {
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IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
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@ -1251,7 +1251,7 @@ void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
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/* Tx queues */
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for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
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iwl3945_tx_queue_free(priv, &priv->txq39[txq_id]);
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iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
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}
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void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
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@ -2342,7 +2342,7 @@ int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
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return 0;
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}
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int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
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int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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int rc;
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unsigned long flags;
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@ -219,9 +219,9 @@ extern void iwl3945_rx_queue_reset(struct iwl_priv *priv,
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extern int iwl3945_calc_db_from_ratio(int sig_ratio);
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extern int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm);
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extern int iwl3945_tx_queue_init(struct iwl_priv *priv,
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struct iwl3945_tx_queue *txq, int count, u32 id);
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struct iwl_tx_queue *txq, int count, u32 id);
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extern void iwl3945_rx_replenish(void *data);
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extern void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq);
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extern void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq);
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extern int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len,
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const void *data);
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extern int __must_check iwl3945_send_cmd(struct iwl_priv *priv,
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@ -270,10 +270,10 @@ extern void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv);
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extern int iwl3945_hw_nic_reset(struct iwl_priv *priv);
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extern int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *tfd,
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dma_addr_t addr, u16 len);
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extern int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq);
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extern int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
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extern int iwl3945_hw_get_temperature(struct iwl_priv *priv);
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extern int iwl3945_hw_tx_queue_init(struct iwl_priv *priv,
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struct iwl3945_tx_queue *txq);
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struct iwl_tx_queue *txq);
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extern unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
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struct iwl3945_frame *frame, u8 rate);
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void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
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@ -114,9 +114,6 @@
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#define RX_QUEUE_MASK 255
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#define RX_QUEUE_SIZE_LOG 8
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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/*
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* RX related structures and functions
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*/
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@ -134,9 +134,13 @@ struct iwl_tx_info {
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*/
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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struct iwl_tx_queue {
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struct iwl_queue q;
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struct iwl_tfd *tfds;
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struct iwl3945_tfd *tfds39;
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struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS];
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struct iwl_tx_info *txb;
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u8 need_update;
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@ -226,28 +230,6 @@ struct iwl_channel_info {
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struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
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};
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/**
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* struct iwl3945_tx_queue - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @bd: base of circular buffer of TFDs
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* @cmd: array of command/Tx buffers
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* @dma_addr_cmd: physical address of cmd/tx buffer array
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* @txb: array of per-TFD driver data
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* @need_update: indicates need to update read/write index
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*/
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struct iwl3945_tx_queue {
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struct iwl_queue q;
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struct iwl3945_tfd *tfds;
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struct iwl_cmd *cmd;
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dma_addr_t dma_addr_cmd;
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struct iwl_tx_info *txb;
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int need_update;
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int active;
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};
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#define IWL_TX_FIFO_AC0 0
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#define IWL_TX_FIFO_AC1 1
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#define IWL_TX_FIFO_AC2 2
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@ -1099,8 +1081,6 @@ struct iwl_priv {
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struct iwl3945_rxon_cmd staging39_rxon;
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struct iwl3945_rxon_cmd recovery39_rxon;
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struct iwl3945_tx_queue txq39[IWL39_MAX_NUM_QUEUES];
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struct iwl3945_power_mgr power_data_39;
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struct iwl3945_notif_statistics statistics_39;
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@ -478,6 +478,17 @@ struct iwl_tfd {
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__le32 __pad;
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} __attribute__ ((packed));
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struct iwl3945_tfd_frame_data {
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__le32 addr;
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__le32 len;
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} __attribute__ ((packed));
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struct iwl3945_tfd_frame {
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__le32 control_flags;
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struct iwl3945_tfd_frame_data pa[4];
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u8 reserved[28];
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} __attribute__ ((packed));
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/* Keep Warm Size */
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#define IWL_KW_SIZE 0x1000 /* 4k */
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@ -57,7 +57,7 @@
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#include "iwl-dev.h"
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static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
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struct iwl3945_tx_queue *txq);
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struct iwl_tx_queue *txq);
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/*
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* module name, copyright, version, etc.
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@ -162,7 +162,7 @@ static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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* iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
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*/
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static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
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struct iwl3945_tx_queue *txq, u32 id)
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struct iwl_tx_queue *txq, u32 id)
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{
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struct pci_dev *dev = priv->pci_dev;
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@ -181,13 +181,13 @@ static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
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/* Circular buffer of transmit frame descriptors (TFDs),
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* shared with device */
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txq->tfds = pci_alloc_consistent(dev,
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sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX,
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txq->tfds39 = pci_alloc_consistent(dev,
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sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
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&txq->q.dma_addr);
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if (!txq->tfds) {
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if (!txq->tfds39) {
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IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
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sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX);
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sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
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goto error;
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}
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txq->q.id = id;
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@ -205,10 +205,9 @@ static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
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* iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
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*/
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int iwl3945_tx_queue_init(struct iwl_priv *priv,
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struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
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struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
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{
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struct pci_dev *dev = priv->pci_dev;
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int len;
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int len, i;
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int rc = 0;
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/*
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@ -219,20 +218,25 @@ int iwl3945_tx_queue_init(struct iwl_priv *priv,
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* For data Tx queues (all other queues), no super-size command
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* space is needed.
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*/
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len = sizeof(struct iwl_cmd) * slots_num;
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if (txq_id == IWL_CMD_QUEUE_NUM)
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len += IWL_MAX_SCAN_SIZE;
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txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
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if (!txq->cmd)
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return -ENOMEM;
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len = sizeof(struct iwl_cmd);
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for (i = 0; i <= slots_num; i++) {
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if (i == slots_num) {
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if (txq_id == IWL_CMD_QUEUE_NUM)
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len += IWL_MAX_SCAN_SIZE;
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else
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continue;
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}
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txq->cmd[i] = kmalloc(len, GFP_KERNEL);
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if (!txq->cmd[i])
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goto err;
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}
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/* Alloc driver data array and TFD circular buffer */
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rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
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if (rc) {
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pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
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if (rc)
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goto err;
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return -ENOMEM;
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}
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txq->need_update = 0;
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/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
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@ -246,6 +250,17 @@ int iwl3945_tx_queue_init(struct iwl_priv *priv,
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iwl3945_hw_tx_queue_init(priv, txq);
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return 0;
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err:
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for (i = 0; i < slots_num; i++) {
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kfree(txq->cmd[i]);
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txq->cmd[i] = NULL;
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}
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if (txq_id == IWL_CMD_QUEUE_NUM) {
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kfree(txq->cmd[slots_num]);
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txq->cmd[slots_num] = NULL;
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}
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return -ENOMEM;
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}
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/**
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@ -256,11 +271,11 @@ int iwl3945_tx_queue_init(struct iwl_priv *priv,
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
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void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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{
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struct iwl_queue *q = &txq->q;
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struct pci_dev *dev = priv->pci_dev;
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int len;
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int len, i;
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if (q->n_bd == 0)
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return;
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@ -275,12 +290,13 @@ void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
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len += IWL_MAX_SCAN_SIZE;
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/* De-alloc array of command/tx buffers */
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pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
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for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd)
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pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
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/* De-alloc array of per-TFD driver data */
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kfree(txq->txb);
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@ -444,7 +460,7 @@ u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flag
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*/
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static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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{
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struct iwl3945_tx_queue *txq = &priv->txq39[IWL_CMD_QUEUE_NUM];
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struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
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struct iwl_queue *q = &txq->q;
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struct iwl3945_tfd *tfd;
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struct iwl_cmd *out_cmd;
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@ -452,7 +468,7 @@ static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
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dma_addr_t phys_addr;
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int pad;
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int ret;
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int ret, len;
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unsigned long flags;
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/* If any of the command structures end up being larger than
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@ -474,11 +490,11 @@ static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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spin_lock_irqsave(&priv->hcmd_lock, flags);
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tfd = &txq->tfds[q->write_ptr];
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tfd = &txq->tfds39[q->write_ptr];
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memset(tfd, 0, sizeof(*tfd));
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idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
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out_cmd = &txq->cmd[idx];
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out_cmd = txq->cmd[idx];
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out_cmd->hdr.cmd = cmd->id;
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memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
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@ -493,8 +509,15 @@ static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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if (out_cmd->meta.flags & CMD_SIZE_HUGE)
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out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
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phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
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offsetof(struct iwl_cmd, hdr);
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len = (idx == TFD_CMD_SLOTS) ?
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IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
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phys_addr = pci_map_single(priv->pci_dev, out_cmd,
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len, PCI_DMA_TODEVICE);
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pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
|
||||
pci_unmap_len_set(&out_cmd->meta, len, len);
|
||||
phys_addr += offsetof(struct iwl_cmd, hdr);
|
||||
|
||||
iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
|
||||
|
||||
pad = U32_PAD(cmd->len);
|
||||
|
|
@ -620,7 +643,7 @@ cancel:
|
|||
* TX cmd queue. Otherwise in case the cmd comes
|
||||
* in later, it will possibly set an invalid
|
||||
* address (cmd->meta.source). */
|
||||
qcmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
|
||||
qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
|
||||
qcmd->meta.flags &= ~CMD_WANT_SKB;
|
||||
}
|
||||
fail:
|
||||
|
|
@ -2229,7 +2252,7 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct iwl3945_tfd *tfd;
|
||||
int txq_id = skb_get_queue_mapping(skb);
|
||||
struct iwl3945_tx_queue *txq = NULL;
|
||||
struct iwl_tx_queue *txq = NULL;
|
||||
struct iwl_queue *q = NULL;
|
||||
dma_addr_t phys_addr;
|
||||
dma_addr_t txcmd_phys;
|
||||
|
|
@ -2306,13 +2329,13 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
}
|
||||
|
||||
/* Descriptor for chosen Tx queue */
|
||||
txq = &priv->txq39[txq_id];
|
||||
txq = &priv->txq[txq_id];
|
||||
q = &txq->q;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
/* Set up first empty TFD within this queue's circular TFD buffer */
|
||||
tfd = &txq->tfds[q->write_ptr];
|
||||
tfd = &txq->tfds39[q->write_ptr];
|
||||
memset(tfd, 0, sizeof(*tfd));
|
||||
idx = get_cmd_index(q, q->write_ptr, 0);
|
||||
|
||||
|
|
@ -2321,7 +2344,7 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
txq->txb[q->write_ptr].skb[0] = skb;
|
||||
|
||||
/* Init first empty entry in queue's array of Tx/cmd buffers */
|
||||
out_cmd = &txq->cmd[idx];
|
||||
out_cmd = txq->cmd[idx];
|
||||
memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
|
||||
memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
|
||||
|
||||
|
|
@ -2360,8 +2383,14 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
|
||||
/* Physical address of this Tx command's header (not MAC header!),
|
||||
* within command buffer array. */
|
||||
txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
|
||||
offsetof(struct iwl_cmd, hdr);
|
||||
txcmd_phys = pci_map_single(priv->pci_dev,
|
||||
out_cmd, sizeof(struct iwl_cmd),
|
||||
PCI_DMA_TODEVICE);
|
||||
pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
|
||||
pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
|
||||
/* Add buffer containing Tx command and MAC(!) header to TFD's
|
||||
* first entry */
|
||||
txcmd_phys += offsetof(struct iwl_cmd, hdr);
|
||||
|
||||
/* Add buffer containing Tx command and MAC(!) header to TFD's
|
||||
* first entry */
|
||||
|
|
@ -3076,7 +3105,7 @@ static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
|
|||
static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
|
||||
int txq_id, int index)
|
||||
{
|
||||
struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
|
||||
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
||||
struct iwl_queue *q = &txq->q;
|
||||
int nfreed = 0;
|
||||
|
||||
|
|
@ -3121,8 +3150,8 @@ static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
|
|||
|
||||
BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
|
||||
|
||||
cmd_index = get_cmd_index(&priv->txq39[IWL_CMD_QUEUE_NUM].q, index, huge);
|
||||
cmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
|
||||
cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
|
||||
cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
|
||||
|
||||
/* Input error checking is done when commands are added to queue. */
|
||||
if (cmd->meta.flags & CMD_WANT_SKB) {
|
||||
|
|
@ -3678,7 +3707,7 @@ static void iwl3945_rx_handle(struct iwl_priv *priv)
|
|||
* iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
|
||||
*/
|
||||
static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
|
||||
struct iwl3945_tx_queue *txq)
|
||||
struct iwl_tx_queue *txq)
|
||||
{
|
||||
u32 reg = 0;
|
||||
int rc = 0;
|
||||
|
|
@ -4088,12 +4117,12 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
|
|||
if (inta & CSR_INT_BIT_WAKEUP) {
|
||||
IWL_DEBUG_ISR("Wakeup interrupt\n");
|
||||
iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[0]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[1]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[2]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[3]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[4]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[5]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
|
||||
iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
|
||||
|
||||
handled |= CSR_INT_BIT_WAKEUP;
|
||||
}
|
||||
|
|
@ -6735,7 +6764,7 @@ static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
|
|||
{
|
||||
struct iwl_priv *priv = hw->priv;
|
||||
int i, avail;
|
||||
struct iwl3945_tx_queue *txq;
|
||||
struct iwl_tx_queue *txq;
|
||||
struct iwl_queue *q;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -6749,7 +6778,7 @@ static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
|
|||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
for (i = 0; i < AC_NUM; i++) {
|
||||
txq = &priv->txq39[i];
|
||||
txq = &priv->txq[i];
|
||||
q = &txq->q;
|
||||
avail = iwl_queue_space(q);
|
||||
|
||||
|
|
|
|||
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