spi: atmel-quadspi: drop wrappers for iomem accesses
The wrappers hid that the accesses are relaxed. Drop them. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -175,17 +175,6 @@ static const struct qspi_mode sama5d2_qspi_modes[] = {
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{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
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};
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/* Register access functions */
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static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
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{
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return readl_relaxed(aq->regs + reg);
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}
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static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
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{
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writel_relaxed(value, aq->regs + reg);
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}
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static inline bool is_compatible(const struct spi_mem_op *op,
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const struct qspi_mode *mode)
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{
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@ -243,7 +232,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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@ -303,17 +292,17 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE;
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/* Clear pending interrupts */
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(void)qspi_readl(aq, QSPI_SR);
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(void)readl_relaxed(aq->regs + QSPI_SR);
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/* Set QSPI Instruction Frame registers */
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qspi_writel(aq, QSPI_IAR, iar);
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qspi_writel(aq, QSPI_ICR, icr);
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qspi_writel(aq, QSPI_IFR, ifr);
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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writel_relaxed(icr, aq->regs + QSPI_ICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)qspi_readl(aq, QSPI_IFR);
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(void)readl_relaxed(aq->regs + QSPI_IFR);
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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@ -324,22 +313,22 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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op->data.buf.out, op->data.nbytes);
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/* Release the chip-select */
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qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
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writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
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}
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/* Poll INSTRuction End status */
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sr = qspi_readl(aq, QSPI_SR);
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sr = readl_relaxed(aq->regs + QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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return err;
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/* Wait for INSTRuction End interrupt */
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reinit_completion(&aq->cmd_completion);
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aq->pending = sr & QSPI_SR_CMD_COMPLETED;
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qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
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if (!wait_for_completion_timeout(&aq->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
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return err;
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}
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@ -378,7 +367,7 @@ static int atmel_qspi_setup(struct spi_device *spi)
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scbr--;
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scr = QSPI_SCR_SCBR(scbr);
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qspi_writel(aq, QSPI_SCR, scr);
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writel_relaxed(scr, aq->regs + QSPI_SCR);
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return 0;
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}
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@ -386,14 +375,14 @@ static int atmel_qspi_setup(struct spi_device *spi)
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static int atmel_qspi_init(struct atmel_qspi *aq)
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{
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/* Reset the QSPI controller */
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qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
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writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
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/* Set the QSPI controller by default in Serial Memory Mode */
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qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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/* Enable the QSPI controller */
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qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
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writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
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return 0;
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}
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@ -403,8 +392,8 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
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struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
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u32 status, mask, pending;
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status = qspi_readl(aq, QSPI_SR);
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mask = qspi_readl(aq, QSPI_IMR);
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status = readl_relaxed(aq->regs + QSPI_SR);
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mask = readl_relaxed(aq->regs + QSPI_IMR);
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pending = status & mask;
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if (!pending)
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@ -510,7 +499,7 @@ static int atmel_qspi_remove(struct platform_device *pdev)
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struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
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spi_unregister_controller(ctrl);
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qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
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writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
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clk_disable_unprepare(aq->clk);
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return 0;
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}
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