ARM: dma-mapping: introduce the idea of buffer ownership
The DMA API has the notion of buffer ownership; make it explicit in the ARM implementation of this API. This gives us a set of hooks to allow us to deal with CPU cache issues arising from non-cache coherent DMA. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-By: Jamie Iles <jamie@jamieiles.com>
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@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
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* We don't need to sync the DMA buffer since
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* it was allocated via the coherent allocators.
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*/
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dma_cache_maint(ptr, size, dir);
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__dma_single_cpu_to_dev(ptr, size, dir);
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}
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return dma_addr;
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@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
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__cpuc_flush_kernel_dcache_area(ptr, size);
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}
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free_safe_buffer(dev->archdata.dmabounce, buf);
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} else {
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__dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
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}
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}
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@ -57,19 +57,48 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
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#endif
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/*
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* DMA-consistent mapping functions. These allocate/free a region of
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* uncached, unwrite-buffered mapped memory space for use with DMA
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* devices. This is the "generic" version. The PCI specific version
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* is in pci.h
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*
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* Note: Drivers should NOT use this function directly, as it will break
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* platforms with CONFIG_DMABOUNCE.
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* Use the driver DMA support - see dma-mapping.h (dma_sync_*)
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* Private support functions: these are not part of the API and are
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* liable to change. Drivers must not use these.
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*/
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extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
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extern void dma_cache_maint_page(struct page *page, unsigned long offset,
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size_t size, int rw);
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/*
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* The DMA API is built upon the notion of "buffer ownership". A buffer
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* is either exclusively owned by the CPU (and therefore may be accessed
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* by it) or exclusively owned by the DMA device. These helper functions
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* represent the transitions between these two ownership states.
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*
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* As above, these are private support functions and not part of the API.
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* Drivers must not use these.
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*/
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static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
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enum dma_data_direction dir)
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{
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if (!arch_is_coherent())
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dma_cache_maint(kaddr, size, dir);
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}
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static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
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enum dma_data_direction dir)
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{
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/* nothing to do */
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}
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static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
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size_t size, enum dma_data_direction dir)
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{
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if (!arch_is_coherent())
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dma_cache_maint_page(page, off, size, dir);
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}
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static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
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size_t size, enum dma_data_direction dir)
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{
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/* nothing to do */
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}
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/*
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* Return whether the given device DMA address mask can be supported
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* properly. For example, if your device can only drive the low 24-bits
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@ -304,8 +333,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
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{
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BUG_ON(!valid_dma_direction(dir));
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if (!arch_is_coherent())
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dma_cache_maint(cpu_addr, size, dir);
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__dma_single_cpu_to_dev(cpu_addr, size, dir);
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return virt_to_dma(dev, cpu_addr);
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}
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@ -329,8 +357,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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{
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BUG_ON(!valid_dma_direction(dir));
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if (!arch_is_coherent())
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dma_cache_maint_page(page, offset, size, dir);
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__dma_page_cpu_to_dev(page, offset, size, dir);
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return page_to_dma(dev, page) + offset;
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}
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@ -352,7 +379,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir)
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{
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/* nothing to do */
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__dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
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}
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/**
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@ -372,7 +399,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
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static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
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size_t size, enum dma_data_direction dir)
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{
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/* nothing to do */
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__dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
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size, dir);
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}
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#endif /* CONFIG_DMABOUNCE */
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@ -400,7 +428,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
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{
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BUG_ON(!valid_dma_direction(dir));
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dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
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if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
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return;
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__dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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@ -412,8 +443,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
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if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
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return;
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if (!arch_is_coherent())
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dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
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__dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
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}
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static inline void dma_sync_single_for_cpu(struct device *dev,
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@ -573,8 +573,12 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int i;
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for_each_sg(sg, s, nents, i) {
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dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
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sg_dma_len(s), dir);
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if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
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sg_dma_len(s), dir))
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continue;
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__dma_page_dev_to_cpu(sg_page(s), s->offset,
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s->length, dir);
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}
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}
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EXPORT_SYMBOL(dma_sync_sg_for_cpu);
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@ -597,9 +601,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
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sg_dma_len(s), dir))
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continue;
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if (!arch_is_coherent())
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dma_cache_maint_page(sg_page(s), s->offset,
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s->length, dir);
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__dma_page_cpu_to_dev(sg_page(s), s->offset,
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s->length, dir);
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}
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}
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EXPORT_SYMBOL(dma_sync_sg_for_device);
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