Merge branch 'ENA-features-and-cosmetic-changes'
Arthur Kiyanovski says: ==================== ENA features and cosmetic changes Diff from V1 of this patchset: Removed error prints patch This patchset includes: 1. new rx offset feature 2. reduction of the driver load time 3. multiple cosmetic changes to the code ==================== Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Коммит
199671eadd
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@ -768,8 +768,8 @@ enum ena_admin_os_type {
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ENA_ADMIN_OS_DPDK = 3,
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ENA_ADMIN_OS_FREEBSD = 4,
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ENA_ADMIN_OS_IPXE = 5,
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ENA_ADMIN_OS_ESXI = 6,
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ENA_ADMIN_OS_GROUPS_NUM = 6,
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ENA_ADMIN_OS_ESXI = 6,
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ENA_ADMIN_OS_GROUPS_NUM = 6,
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};
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struct ena_admin_host_info {
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@ -813,7 +813,8 @@ struct ena_admin_host_info {
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u16 reserved;
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/* 1 :0 : reserved
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/* 0 : reserved
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* 1 : rx_offset
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* 2 : interrupt_moderation
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* 31:3 : reserved
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*/
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@ -1124,6 +1125,8 @@ struct ena_admin_ena_mmio_req_read_less_resp {
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#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
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#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
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#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
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@ -1133,4 +1136,4 @@ struct ena_admin_ena_mmio_req_read_less_resp {
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/* aenq_link_change_desc */
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#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
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#endif /*_ENA_ADMIN_H_ */
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#endif /* _ENA_ADMIN_H_ */
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@ -62,7 +62,9 @@
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#define ENA_REGS_ADMIN_INTR_MASK 1
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#define ENA_POLL_MS 5
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#define ENA_MIN_ADMIN_POLL_US 100
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#define ENA_MAX_ADMIN_POLL_US 5000
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/*****************************************************************************/
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/*****************************************************************************/
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@ -200,17 +202,17 @@ static void comp_ctxt_release(struct ena_com_admin_queue *queue,
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static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
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u16 command_id, bool capture)
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{
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if (unlikely(!queue->comp_ctx)) {
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pr_err("Completion context is NULL\n");
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return NULL;
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}
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if (unlikely(command_id >= queue->q_depth)) {
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pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
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command_id, queue->q_depth);
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return NULL;
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}
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if (unlikely(!queue->comp_ctx)) {
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pr_err("Completion context is NULL\n");
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return NULL;
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}
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if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
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pr_err("Completion context is occupied\n");
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return NULL;
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@ -375,7 +377,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
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io_sq->bounce_buf_ctrl.next_to_use = 0;
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size = io_sq->bounce_buf_ctrl.buffer_size *
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io_sq->bounce_buf_ctrl.buffers_num;
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io_sq->bounce_buf_ctrl.buffers_num;
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dev_node = dev_to_node(ena_dev->dmadev);
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set_dev_node(ena_dev->dmadev, ctx->numa_node);
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@ -523,9 +525,6 @@ static int ena_com_comp_status_to_errno(u8 comp_status)
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if (unlikely(comp_status != 0))
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pr_err("admin command failed[%u]\n", comp_status);
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if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
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return -EINVAL;
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switch (comp_status) {
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case ENA_ADMIN_SUCCESS:
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return 0;
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@ -540,7 +539,14 @@ static int ena_com_comp_status_to_errno(u8 comp_status)
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return -EINVAL;
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}
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return 0;
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return -EINVAL;
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}
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static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
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{
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delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
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delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
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usleep_range(delay_us, 2 * delay_us);
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}
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static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
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@ -549,6 +555,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c
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unsigned long flags = 0;
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unsigned long timeout;
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int ret;
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u32 exp = 0;
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timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
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@ -572,7 +579,8 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c
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goto err;
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}
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msleep(ENA_POLL_MS);
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ena_delay_exponential_backoff_us(exp++,
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admin_queue->ena_dev->ena_min_poll_delay_us);
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}
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if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
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@ -702,8 +710,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
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/* The desc list entry size should be whole multiply of 8
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* This requirement comes from __iowrite64_copy()
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*/
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pr_err("illegal entry size %d\n",
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llq_info->desc_list_entry_size);
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pr_err("illegal entry size %d\n", llq_info->desc_list_entry_size);
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return -EINVAL;
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}
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@ -775,7 +782,7 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com
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if (admin_queue->auto_polling)
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admin_queue->polling = true;
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} else {
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pr_err("The ena device doesn't send a completion for the admin cmd %d status %d\n",
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pr_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
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comp_ctx->cmd_opcode, comp_ctx->status);
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}
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/* Check if shifted to polling mode.
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@ -943,12 +950,13 @@ static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
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static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
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u16 exp_state)
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{
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u32 val, i;
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u32 val, exp = 0;
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unsigned long timeout_stamp;
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/* Convert timeout from resolution of 100ms to ENA_POLL_MS */
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timeout = (timeout * 100) / ENA_POLL_MS;
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/* Convert timeout from resolution of 100ms to us resolution. */
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timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
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for (i = 0; i < timeout; i++) {
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while (1) {
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val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
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if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
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@ -960,10 +968,11 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
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exp_state)
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return 0;
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msleep(ENA_POLL_MS);
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}
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if (time_is_before_jiffies(timeout_stamp))
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return -ETIME;
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return -ETIME;
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ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
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}
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}
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static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
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@ -1284,13 +1293,9 @@ static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
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static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
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u16 intr_delay_resolution)
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{
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/* Initial value of intr_delay_resolution might be 0 */
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u16 prev_intr_delay_resolution =
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ena_dev->intr_delay_resolution ?
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ena_dev->intr_delay_resolution :
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ENA_DEFAULT_INTR_DELAY_RESOLUTION;
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u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
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if (!intr_delay_resolution) {
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if (unlikely(!intr_delay_resolution)) {
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pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
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intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
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}
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@ -1444,11 +1449,13 @@ void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
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{
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struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
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unsigned long flags = 0;
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u32 exp = 0;
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spin_lock_irqsave(&admin_queue->q_lock, flags);
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while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
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spin_unlock_irqrestore(&admin_queue->q_lock, flags);
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msleep(ENA_POLL_MS);
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ena_delay_exponential_backoff_us(exp++,
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ena_dev->ena_min_poll_delay_us);
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spin_lock_irqsave(&admin_queue->q_lock, flags);
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}
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spin_unlock_irqrestore(&admin_queue->q_lock, flags);
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@ -1796,6 +1803,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,
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if (ret)
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goto error;
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admin_queue->ena_dev = ena_dev;
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admin_queue->running_state = true;
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return 0;
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@ -2003,7 +2011,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
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struct ena_admin_aenq_entry *aenq_e;
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struct ena_admin_aenq_common_desc *aenq_common;
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struct ena_com_aenq *aenq = &dev->aenq;
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unsigned long long timestamp;
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u64 timestamp;
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ena_aenq_handler handler_cb;
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u16 masked_head, processed = 0;
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u8 phase;
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@ -2021,9 +2029,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
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*/
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dma_rmb();
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timestamp =
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(unsigned long long)aenq_common->timestamp_low |
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((unsigned long long)aenq_common->timestamp_high << 32);
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timestamp = (u64)aenq_common->timestamp_low |
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((u64)aenq_common->timestamp_high << 32);
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pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
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aenq_common->group, aenq_common->syndrom, timestamp);
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@ -2053,8 +2060,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
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/* write the aenq doorbell after all AENQ descriptors were read */
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mb();
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writel_relaxed((u32)aenq->head,
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dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
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writel_relaxed((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
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}
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int ena_com_dev_reset(struct ena_com_dev *ena_dev,
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@ -2276,13 +2282,14 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
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enum ena_admin_hash_functions func,
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const u8 *key, u16 key_len, u32 init_val)
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{
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struct ena_rss *rss = &ena_dev->rss;
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struct ena_admin_feature_rss_flow_hash_control *hash_key;
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struct ena_admin_get_feat_resp get_resp;
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struct ena_admin_feature_rss_flow_hash_control *hash_key =
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rss->hash_key;
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enum ena_admin_hash_functions old_func;
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struct ena_rss *rss = &ena_dev->rss;
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int rc;
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hash_key = rss->hash_key;
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/* Make sure size is a mult of DWs */
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if (unlikely(key_len & 0x3))
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return -EINVAL;
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@ -2294,7 +2301,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
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if (unlikely(rc))
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return rc;
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if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
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if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
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pr_err("Flow hash function %d isn't supported\n", func);
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return -EOPNOTSUPP;
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}
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@ -77,6 +77,8 @@
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#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0
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#define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
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#define ENA_HASH_KEY_SIZE 40
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#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
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#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
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@ -237,6 +239,7 @@ struct ena_com_stats_admin {
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struct ena_com_admin_queue {
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void *q_dmadev;
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struct ena_com_dev *ena_dev;
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spinlock_t q_lock; /* spinlock for the admin queue */
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struct ena_comp_ctx *comp_ctx;
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@ -349,6 +352,8 @@ struct ena_com_dev {
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struct ena_intr_moder_entry *intr_moder_tbl;
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struct ena_com_llq_info llq_info;
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u32 ena_min_poll_delay_us;
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};
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struct ena_com_dev_get_features_ctx {
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@ -393,7 +398,7 @@ struct ena_aenq_handlers {
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*/
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int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
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/* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
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/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism
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* @ena_dev: ENA communication layer struct
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* @readless_supported: readless mode (enable/disable)
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*/
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@ -515,7 +520,7 @@ void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
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/* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
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* @ena_dev: ENA communication layer struct
|
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*
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* This method go over the admin completion queue and wake up all the pending
|
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* This method goes over the admin completion queue and wakes up all the pending
|
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* threads that wait on the commands wait event.
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*
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* @note: Should be called after MSI-X interrupt.
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@ -525,7 +530,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
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/* ena_com_aenq_intr_handler - AENQ interrupt handler
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* @ena_dev: ENA communication layer struct
|
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*
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* This method go over the async event notification queue and call the proper
|
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* This method goes over the async event notification queue and calls the proper
|
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* aenq handler.
|
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*/
|
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void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
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@ -542,14 +547,14 @@ void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
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/* ena_com_wait_for_abort_completion - Wait for admin commands abort.
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* @ena_dev: ENA communication layer struct
|
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*
|
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* This method wait until all the outstanding admin commands will be completed.
|
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* This method waits until all the outstanding admin commands are completed.
|
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*/
|
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void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
|
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|
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/* ena_com_validate_version - Validate the device parameters
|
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* @ena_dev: ENA communication layer struct
|
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*
|
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* This method validate the device parameters are the same as the saved
|
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* This method verifies the device parameters are the same as the saved
|
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* parameters in ena_dev.
|
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* This method is useful after device reset, to validate the device mac address
|
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* and the device offloads are the same as before the reset.
|
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|
@ -689,7 +694,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
|
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*
|
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* Retrieve the hash function from the device.
|
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*
|
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* @note: If the caller called ena_com_fill_hash_function but didn't flash
|
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* @note: If the caller called ena_com_fill_hash_function but didn't flush
|
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* it to the device, the new configuration will be lost.
|
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*
|
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* @return: 0 on Success and negative value otherwise.
|
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|
@ -703,7 +708,7 @@ int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
|
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*
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* Retrieve the hash key.
|
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*
|
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* @note: If the caller called ena_com_fill_hash_key but didn't flash
|
||||
* @note: If the caller called ena_com_fill_hash_key but didn't flush
|
||||
* it to the device, the new configuration will be lost.
|
||||
*
|
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* @return: 0 on Success and negative value otherwise.
|
||||
|
@ -743,7 +748,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
|
|||
*
|
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* Retrieve the hash control from the device.
|
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*
|
||||
* @note, If the caller called ena_com_fill_hash_ctrl but didn't flash
|
||||
* @note: If the caller called ena_com_fill_hash_ctrl but didn't flush
|
||||
* it to the device, the new configuration will be lost.
|
||||
*
|
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* @return: 0 on Success and negative value otherwise.
|
||||
|
@ -795,7 +800,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
|
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*
|
||||
* Retrieve the RSS indirection table from the device.
|
||||
*
|
||||
* @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
|
||||
* @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush
|
||||
* it to the device, the new configuration will be lost.
|
||||
*
|
||||
* @return: 0 on Success and negative value otherwise.
|
||||
|
@ -821,14 +826,14 @@ int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
|
|||
/* ena_com_delete_debug_area - Free the debug area resources.
|
||||
* @ena_dev: ENA communication layer struct
|
||||
*
|
||||
* Free the allocate debug area.
|
||||
* Free the allocated debug area.
|
||||
*/
|
||||
void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
|
||||
|
||||
/* ena_com_delete_host_info - Free the host info resources.
|
||||
* @ena_dev: ENA communication layer struct
|
||||
*
|
||||
* Free the allocate host info.
|
||||
* Free the allocated host info.
|
||||
*/
|
||||
void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
|
||||
|
||||
|
@ -869,9 +874,9 @@ int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
|
|||
* @cmd_completion: command completion return value.
|
||||
* @cmd_comp_size: command completion size.
|
||||
|
||||
* Submit an admin command and then wait until the device will return a
|
||||
* Submit an admin command and then wait until the device returns a
|
||||
* completion.
|
||||
* The completion will be copyed into cmd_comp.
|
||||
* The completion will be copied into cmd_comp.
|
||||
*
|
||||
* @return - 0 on success, negative value on failure.
|
||||
*/
|
||||
|
@ -934,7 +939,7 @@ unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *
|
|||
/* ena_com_config_dev_mode - Configure the placement policy of the device.
|
||||
* @ena_dev: ENA communication layer struct
|
||||
* @llq_features: LLQ feature descriptor, retrieve via
|
||||
* ena_com_get_dev_attr_feat.
|
||||
* ena_com_get_dev_attr_feat.
|
||||
* @ena_llq_config: The default driver LLQ parameters configurations
|
||||
*/
|
||||
int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
|
||||
|
@ -960,7 +965,7 @@ static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_d
|
|||
* @intr_reg: interrupt register to update.
|
||||
* @rx_delay_interval: Rx interval in usecs
|
||||
* @tx_delay_interval: Tx interval in usecs
|
||||
* @unmask: unask enable/disable
|
||||
* @unmask: unmask enable/disable
|
||||
*
|
||||
* Prepare interrupt update register with the supplied parameters.
|
||||
*/
|
||||
|
|
|
@ -45,4 +45,4 @@ struct ena_common_mem_addr {
|
|||
u16 reserved16;
|
||||
};
|
||||
|
||||
#endif /*_ENA_COMMON_H_ */
|
||||
#endif /* _ENA_COMMON_H_ */
|
||||
|
|
|
@ -519,7 +519,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
|
|||
struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
|
||||
u16 cdesc_idx = 0;
|
||||
u16 nb_hw_desc;
|
||||
u16 i;
|
||||
u16 i = 0;
|
||||
|
||||
WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type");
|
||||
|
||||
|
@ -538,13 +538,19 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
|
|||
return -ENOSPC;
|
||||
}
|
||||
|
||||
for (i = 0; i < nb_hw_desc; i++) {
|
||||
cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx);
|
||||
ena_rx_ctx->pkt_offset = cdesc->offset;
|
||||
|
||||
do {
|
||||
ena_buf[i].len = cdesc->length;
|
||||
ena_buf[i].req_id = cdesc->req_id;
|
||||
|
||||
if (++i >= nb_hw_desc)
|
||||
break;
|
||||
|
||||
cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
|
||||
|
||||
ena_buf->len = cdesc->length;
|
||||
ena_buf->req_id = cdesc->req_id;
|
||||
ena_buf++;
|
||||
}
|
||||
} while (1);
|
||||
|
||||
/* Update SQ head ptr */
|
||||
io_sq->next_to_comp += nb_hw_desc;
|
||||
|
@ -578,10 +584,10 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
|
|||
|
||||
desc->length = ena_buf->len;
|
||||
|
||||
desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK;
|
||||
desc->ctrl |= ENA_ETH_IO_RX_DESC_LAST_MASK;
|
||||
desc->ctrl |= io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK;
|
||||
desc->ctrl |= ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
|
||||
desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
|
||||
ENA_ETH_IO_RX_DESC_LAST_MASK |
|
||||
(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |
|
||||
ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
|
||||
|
||||
desc->req_id = req_id;
|
||||
|
||||
|
|
|
@ -73,6 +73,7 @@ struct ena_com_rx_ctx {
|
|||
u32 hash;
|
||||
u16 descs;
|
||||
int max_bufs;
|
||||
u8 pkt_offset;
|
||||
};
|
||||
|
||||
int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
|
@ -95,7 +96,7 @@ static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
|
|||
writel(intr_reg->intr_control, io_cq->unmask_reg);
|
||||
}
|
||||
|
||||
static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)
|
||||
static inline int ena_com_free_q_entries(struct ena_com_io_sq *io_sq)
|
||||
{
|
||||
u16 tail, next_to_comp, cnt;
|
||||
|
||||
|
@ -113,7 +114,7 @@ static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
|
|||
int temp;
|
||||
|
||||
if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
|
||||
return ena_com_free_desc(io_sq) >= required_buffers;
|
||||
return ena_com_free_q_entries(io_sq) >= required_buffers;
|
||||
|
||||
/* This calculation doesn't need to be 100% accurate. So to reduce
|
||||
* the calculation overhead just Subtract 2 lines from the free descs
|
||||
|
@ -122,7 +123,7 @@ static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
|
|||
*/
|
||||
temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
|
||||
|
||||
return ena_com_free_desc(io_sq) > temp;
|
||||
return ena_com_free_q_entries(io_sq) > temp;
|
||||
}
|
||||
|
||||
static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
|
||||
|
|
|
@ -264,7 +264,9 @@ struct ena_eth_io_rx_cdesc_base {
|
|||
|
||||
u16 sub_qid;
|
||||
|
||||
u16 reserved;
|
||||
u8 offset;
|
||||
|
||||
u8 reserved;
|
||||
};
|
||||
|
||||
/* 8-word format */
|
||||
|
@ -412,4 +414,4 @@ struct ena_eth_io_numa_node_cfg_reg {
|
|||
#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
|
||||
#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
|
||||
|
||||
#endif /*_ENA_ETH_IO_H_ */
|
||||
#endif /* _ENA_ETH_IO_H_ */
|
||||
|
|
|
@ -206,7 +206,7 @@ int ena_get_sset_count(struct net_device *netdev, int sset)
|
|||
if (sset != ETH_SS_STATS)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return adapter->num_io_queues * (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX)
|
||||
return adapter->num_io_queues * (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX)
|
||||
+ ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
|
||||
}
|
||||
|
||||
|
@ -260,7 +260,6 @@ static void ena_get_strings(struct net_device *netdev, u32 sset, u8 *data)
|
|||
|
||||
for (i = 0; i < ENA_STATS_ARRAY_GLOBAL; i++) {
|
||||
ena_stats = &ena_stats_global_strings[i];
|
||||
|
||||
memcpy(data, ena_stats->name, ETH_GSTRING_LEN);
|
||||
data += ETH_GSTRING_LEN;
|
||||
}
|
||||
|
@ -307,10 +306,8 @@ static int ena_get_coalesce(struct net_device *net_dev,
|
|||
struct ena_adapter *adapter = netdev_priv(net_dev);
|
||||
struct ena_com_dev *ena_dev = adapter->ena_dev;
|
||||
|
||||
if (!ena_com_interrupt_moderation_supported(ena_dev)) {
|
||||
/* the devie doesn't support interrupt moderation */
|
||||
if (!ena_com_interrupt_moderation_supported(ena_dev))
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
coalesce->tx_coalesce_usecs =
|
||||
ena_com_get_nonadaptive_moderation_interval_tx(ena_dev) *
|
||||
|
@ -326,7 +323,7 @@ static int ena_get_coalesce(struct net_device *net_dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void ena_update_tx_rings_intr_moderation(struct ena_adapter *adapter)
|
||||
static void ena_update_tx_rings_nonadaptive_intr_moderation(struct ena_adapter *adapter)
|
||||
{
|
||||
unsigned int val;
|
||||
int i;
|
||||
|
@ -337,7 +334,7 @@ static void ena_update_tx_rings_intr_moderation(struct ena_adapter *adapter)
|
|||
adapter->tx_ring[i].smoothed_interval = val;
|
||||
}
|
||||
|
||||
static void ena_update_rx_rings_intr_moderation(struct ena_adapter *adapter)
|
||||
static void ena_update_rx_rings_nonadaptive_intr_moderation(struct ena_adapter *adapter)
|
||||
{
|
||||
unsigned int val;
|
||||
int i;
|
||||
|
@ -355,24 +352,22 @@ static int ena_set_coalesce(struct net_device *net_dev,
|
|||
struct ena_com_dev *ena_dev = adapter->ena_dev;
|
||||
int rc;
|
||||
|
||||
if (!ena_com_interrupt_moderation_supported(ena_dev)) {
|
||||
/* the devie doesn't support interrupt moderation */
|
||||
if (!ena_com_interrupt_moderation_supported(ena_dev))
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
rc = ena_com_update_nonadaptive_moderation_interval_tx(ena_dev,
|
||||
coalesce->tx_coalesce_usecs);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
ena_update_tx_rings_intr_moderation(adapter);
|
||||
ena_update_tx_rings_nonadaptive_intr_moderation(adapter);
|
||||
|
||||
rc = ena_com_update_nonadaptive_moderation_interval_rx(ena_dev,
|
||||
coalesce->rx_coalesce_usecs);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
ena_update_rx_rings_intr_moderation(adapter);
|
||||
ena_update_rx_rings_nonadaptive_intr_moderation(adapter);
|
||||
|
||||
if (coalesce->use_adaptive_rx_coalesce &&
|
||||
!ena_com_get_adaptive_moderation_enabled(ena_dev))
|
||||
|
|
|
@ -1435,6 +1435,8 @@ static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
|
|||
|
||||
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
|
||||
rx_info->page_offset, len, ENA_PAGE_SIZE);
|
||||
/* The offset is non zero only for the first buffer */
|
||||
rx_info->page_offset = 0;
|
||||
|
||||
netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
|
||||
"rx skb updated. len %d. data_len %d\n",
|
||||
|
@ -1590,6 +1592,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
|
|||
{
|
||||
u16 next_to_clean = rx_ring->next_to_clean;
|
||||
struct ena_com_rx_ctx ena_rx_ctx;
|
||||
struct ena_rx_buffer *rx_info;
|
||||
struct ena_adapter *adapter;
|
||||
u32 res_budget, work_done;
|
||||
int rx_copybreak_pkt = 0;
|
||||
|
@ -1614,6 +1617,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
|
|||
ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
|
||||
ena_rx_ctx.max_bufs = rx_ring->sgl_size;
|
||||
ena_rx_ctx.descs = 0;
|
||||
ena_rx_ctx.pkt_offset = 0;
|
||||
rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
|
||||
rx_ring->ena_com_io_sq,
|
||||
&ena_rx_ctx);
|
||||
|
@ -1623,6 +1627,9 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
|
|||
if (unlikely(ena_rx_ctx.descs == 0))
|
||||
break;
|
||||
|
||||
rx_info = &rx_ring->rx_buffer_info[rx_ring->ena_bufs[0].req_id];
|
||||
rx_info->page_offset = ena_rx_ctx.pkt_offset;
|
||||
|
||||
netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
|
||||
"rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
|
||||
rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
|
||||
|
@ -1684,7 +1691,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
|
|||
|
||||
rx_ring->next_to_clean = next_to_clean;
|
||||
|
||||
refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq);
|
||||
refill_required = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
|
||||
refill_threshold =
|
||||
min_t(int, rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER,
|
||||
ENA_RX_REFILL_THRESH_PACKET);
|
||||
|
@ -2235,7 +2242,7 @@ static int ena_rss_configure(struct ena_adapter *adapter)
|
|||
rc = ena_rss_init_default(adapter);
|
||||
if (rc && (rc != -EOPNOTSUPP)) {
|
||||
netif_err(adapter, ifup, adapter->netdev,
|
||||
"Failed to init RSS rc: %d\n", rc);
|
||||
"Failed to init RSS rc: %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
@ -2308,7 +2315,7 @@ static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
|
|||
if (rc) {
|
||||
netif_err(adapter, ifup, adapter->netdev,
|
||||
"Failed to create I/O TX queue num %d rc: %d\n",
|
||||
qid, rc);
|
||||
qid, rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
@ -2457,7 +2464,7 @@ static int create_queues_with_size_backoff(struct ena_adapter *adapter)
|
|||
* ones due to past queue allocation failures.
|
||||
*/
|
||||
set_io_rings_size(adapter, adapter->requested_tx_ring_size,
|
||||
adapter->requested_rx_ring_size);
|
||||
adapter->requested_rx_ring_size);
|
||||
|
||||
while (1) {
|
||||
if (ena_xdp_present(adapter)) {
|
||||
|
@ -2498,7 +2505,7 @@ err_setup_tx:
|
|||
if (rc != -ENOMEM) {
|
||||
netif_err(adapter, ifup, adapter->netdev,
|
||||
"Queue creation failed with error code %d\n",
|
||||
rc);
|
||||
rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
@ -2521,7 +2528,7 @@ err_setup_tx:
|
|||
new_rx_ring_size = cur_rx_ring_size / 2;
|
||||
|
||||
if (new_tx_ring_size < ENA_MIN_RING_SIZE ||
|
||||
new_rx_ring_size < ENA_MIN_RING_SIZE) {
|
||||
new_rx_ring_size < ENA_MIN_RING_SIZE) {
|
||||
netif_err(adapter, ifup, adapter->netdev,
|
||||
"Queue creation failed with the smallest possible queue size of %d for both queues. Not retrying with smaller queues\n",
|
||||
ENA_MIN_RING_SIZE);
|
||||
|
@ -3080,8 +3087,7 @@ static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
|
|||
return qid;
|
||||
}
|
||||
|
||||
static void ena_config_host_info(struct ena_com_dev *ena_dev,
|
||||
struct pci_dev *pdev)
|
||||
static void ena_config_host_info(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
|
||||
{
|
||||
struct ena_admin_host_info *host_info;
|
||||
int rc;
|
||||
|
@ -3111,6 +3117,7 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev,
|
|||
host_info->num_cpus = num_online_cpus();
|
||||
|
||||
host_info->driver_supported_features =
|
||||
ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
|
||||
ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
|
||||
|
||||
rc = ena_com_set_host_attributes(ena_dev);
|
||||
|
@ -3686,8 +3693,7 @@ static void check_for_empty_rx_ring(struct ena_adapter *adapter)
|
|||
for (i = 0; i < adapter->num_io_queues; i++) {
|
||||
rx_ring = &adapter->rx_ring[i];
|
||||
|
||||
refill_required =
|
||||
ena_com_free_desc(rx_ring->ena_com_io_sq);
|
||||
refill_required = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
|
||||
if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
|
||||
rx_ring->empty_rx_queue++;
|
||||
|
||||
|
@ -3825,11 +3831,11 @@ static void ena_timer_service(struct timer_list *t)
|
|||
mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
|
||||
}
|
||||
|
||||
static int ena_calc_max_io_queue_num(struct pci_dev *pdev,
|
||||
static u32 ena_calc_max_io_queue_num(struct pci_dev *pdev,
|
||||
struct ena_com_dev *ena_dev,
|
||||
struct ena_com_dev_get_features_ctx *get_feat_ctx)
|
||||
{
|
||||
int io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
|
||||
u32 io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
|
||||
|
||||
if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
|
||||
struct ena_admin_queue_ext_feature_fields *max_queue_ext =
|
||||
|
@ -4115,8 +4121,8 @@ static int ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx)
|
|||
*/
|
||||
static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
struct ena_com_dev_get_features_ctx get_feat_ctx;
|
||||
struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
|
||||
struct ena_com_dev_get_features_ctx get_feat_ctx;
|
||||
struct ena_llq_configurations llq_config;
|
||||
struct ena_com_dev *ena_dev = NULL;
|
||||
struct ena_adapter *adapter;
|
||||
|
@ -4160,6 +4166,8 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
goto err_free_region;
|
||||
}
|
||||
|
||||
ena_dev->ena_min_poll_delay_us = ENA_ADMIN_POLL_DELAY_US;
|
||||
|
||||
ena_dev->dmadev = &pdev->dev;
|
||||
|
||||
rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
|
||||
|
@ -4183,7 +4191,7 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
|
||||
calc_queue_ctx.pdev = pdev;
|
||||
|
||||
/* Initial Tx and RX interrupt delay. Assumes 1 usec granularity.
|
||||
/* Initial TX and RX interrupt delay. Assumes 1 usec granularity.
|
||||
* Updated during device initialization with the real granularity
|
||||
*/
|
||||
ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
|
||||
|
@ -4227,12 +4235,11 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
|
||||
adapter->num_io_queues = max_num_io_queues;
|
||||
adapter->max_num_io_queues = max_num_io_queues;
|
||||
adapter->last_monitored_tx_qid = 0;
|
||||
|
||||
adapter->xdp_first_ring = 0;
|
||||
adapter->xdp_num_queues = 0;
|
||||
|
||||
adapter->last_monitored_tx_qid = 0;
|
||||
|
||||
adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
|
||||
adapter->wd_state = wd_state;
|
||||
|
||||
|
|
|
@ -50,12 +50,6 @@
|
|||
#define DRV_MODULE_GEN_SUBMINOR 0
|
||||
|
||||
#define DRV_MODULE_NAME "ena"
|
||||
#ifndef DRV_MODULE_GENERATION
|
||||
#define DRV_MODULE_GENERATION \
|
||||
__stringify(DRV_MODULE_GEN_MAJOR) "." \
|
||||
__stringify(DRV_MODULE_GEN_MINOR) "." \
|
||||
__stringify(DRV_MODULE_GEN_SUBMINOR) "K"
|
||||
#endif
|
||||
|
||||
#define DEVICE_NAME "Elastic Network Adapter (ENA)"
|
||||
|
||||
|
@ -104,8 +98,6 @@
|
|||
#define ENA_RX_RSS_TABLE_LOG_SIZE 7
|
||||
#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
|
||||
|
||||
#define ENA_HASH_KEY_SIZE 40
|
||||
|
||||
/* The number of tx packet completions that will be handled each NAPI poll
|
||||
* cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
|
||||
*/
|
||||
|
@ -137,6 +129,8 @@
|
|||
#define ENA_IO_IRQ_FIRST_IDX 1
|
||||
#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
|
||||
|
||||
#define ENA_ADMIN_POLL_DELAY_US 100
|
||||
|
||||
/* ENA device should send keep alive msg every 1 sec.
|
||||
* We wait for 6 sec just to be on the safe side.
|
||||
*/
|
||||
|
|
|
@ -154,4 +154,4 @@ enum ena_regs_reset_reason_types {
|
|||
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
|
||||
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
|
||||
|
||||
#endif /*_ENA_REGS_H_ */
|
||||
#endif /* _ENA_REGS_H_ */
|
||||
|
|
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