Late omap dts changes for v5.6 merge window
This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl4rTjIRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNPIxAAsx6cR/yzoEvUv1fGFi44Y/VZEhfI/8yT 5esGWql/UINkyTLBTsME6liDTt7rAVxcHH1JQj04hYH/w/PQU8S4iu8ZVwxoAb9R Mmnfn8Py26scney0zseJc6tTTDbtXF+mxDBYUqAJNKjDyoRkJKxWtMMOHUC7WjVW P5E4uWgi2ydEFgn6hOzLORgHPtNnOWPdXYzKvmum7VZdRny7KHcuOk4kVFnj3dzG RwGrsOQcs2EyHd08n+U3tZqk34JqhOWi2VAKPZTHVlsZOdDKU9hm45ZSDh/j7Xoy 74x2ux81guKBAtgpKSJR5TUottgPM5IdnnyCmKkDgF7AWySByeJYPOVWyxwZuSQD tCmCi9fFSXCogoijMvSFPbcsKI/u6UKHYIOS9zvJo70FxNVTckhzjTH+DRQpjrTB oEAfpCS56bHUUYvPomDvxRT87kLlcs/A6g8+puRKd2xa3dmsXkTKeppuEBIC6WKE JtZYGsvWSe0gSVscsrE3Ecf17jS2O7Yhy3/4eOHJzUgsIGn8xcjuJJO3Av+bFj87 kDF66tRKR6LcKD1S6v5a87hmKD3rxkj23LUEvS0bWsOVLmgqIQYeZYpR5ujkRLxC 1NlzWFVqBtCMe6qPRz7FaitrdZlTaMURRD0GXSQmZCsTrSVrghUTJBZw92ep2kWD rIwSzpB1p08= =u4PK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Коммит
19d52e94e0
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@ -691,6 +691,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
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omap3-devkit8000.dtb \
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omap3-devkit8000-lcd43.dtb \
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omap3-devkit8000-lcd70.dtb \
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omap3-echo.dtb \
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omap3-evm.dtb \
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omap3-evm-37xx.dtb \
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omap3-gta04a3.dtb \
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@ -113,7 +113,7 @@
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};
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};
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backlight {
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&ecap0 0 50000 0>;
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brightness-levels = <0 51 53 56 62 75 101 152 255>;
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@ -121,35 +121,15 @@
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};
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panel {
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compatible = "ti,tilcdc,panel";
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status = "okay";
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compatible = "tfc,s9700rtwv43tr-01b";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins_s0>;
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panel-info {
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ac-bias = <255>;
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ac-bias-intrpt = <0>;
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dma-burst-sz = <16>;
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bpp = <32>;
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fdd = <0x80>;
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sync-edge = <0>;
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sync-ctrl = <1>;
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raster-order = <0>;
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fifo-th = <0>;
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};
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backlight = <&backlight>;
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display-timings {
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800x480p62 {
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clock-frequency = <30000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <39>;
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hback-porch = <39>;
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hsync-len = <47>;
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vback-porch = <29>;
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vfront-porch = <13>;
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vsync-len = <2>;
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hsync-active = <1>;
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vsync-active = <1>;
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port {
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panel_0: endpoint@0 {
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remote-endpoint = <&lcdc_0>;
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};
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};
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};
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@ -500,6 +480,12 @@
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status = "okay";
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blue-and-red-wiring = "crossed";
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port {
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lcdc_0: endpoint@0 {
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remote-endpoint = <&panel_0>;
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};
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};
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};
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&elm {
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@ -183,36 +183,16 @@
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};
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panel {
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compatible = "ti,tilcdc,panel";
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compatible = "newhaven,nhd-4.3-480272ef-atxl";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&lcd_pins_default>;
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pinctrl-1 = <&lcd_pins_sleep>;
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backlight = <&lcd_bl>;
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status = "okay";
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panel-info {
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ac-bias = <255>;
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ac-bias-intrpt = <0>;
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dma-burst-sz = <16>;
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bpp = <32>;
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fdd = <0x80>;
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sync-edge = <0>;
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sync-ctrl = <1>;
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raster-order = <0>;
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fifo-th = <0>;
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};
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display-timings {
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480x272 {
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hactive = <480>;
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vactive = <272>;
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hback-porch = <43>;
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hfront-porch = <8>;
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hsync-len = <4>;
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vback-porch = <12>;
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vfront-porch = <4>;
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vsync-len = <10>;
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clock-frequency = <9000000>;
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hsync-active = <0>;
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vsync-active = <0>;
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port {
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panel_0: endpoint@0 {
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remote-endpoint = <&lcdc_0>;
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};
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};
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};
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@ -725,6 +705,12 @@
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status = "okay";
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blue-and-red-wiring = "crossed";
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port {
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lcdc_0: endpoint@0 {
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remote-endpoint = <&panel_0>;
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};
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};
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};
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&rtc {
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@ -287,6 +287,19 @@
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gpio-controller;
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#gpio-cells = <2>;
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};
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/* osd9616p0899-10 */
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display@3c {
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compatible = "solomon,ssd1306fb-i2c";
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reg = <0x3c>;
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solomon,height = <16>;
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solomon,width = <96>;
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solomon,com-seq;
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solomon,com-invdir;
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solomon,page-offset = <0>;
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solomon,prechargep1 = <2>;
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solomon,prechargep2 = <13>;
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};
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};
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&spi0 {
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@ -496,6 +496,31 @@
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dma-names = "tx", "rx";
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};
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};
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target-module@56000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5600fe00 0x4>,
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<0x5600fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_gfx 0>;
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reset-names = "rstctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x56000000 0x1000000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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};
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};
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@ -74,7 +74,7 @@
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clock-names = "ick";
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};
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davinci_mdio: ethernet@5c030000 {
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davinci_mdio: mdio@5c030000 {
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compatible = "ti,davinci_mdio";
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ti,hwmods = "davinci_mdio";
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status = "disabled";
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@ -0,0 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
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*/
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#include "omap36xx.dtsi"
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&iva {
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status = "disabled";
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};
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&sgx_module {
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status = "disabled";
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};
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@ -0,0 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
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*/
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#include "omap36xx.dtsi"
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&iva {
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status = "disabled";
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};
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@ -445,6 +445,26 @@
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pool;
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};
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};
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target-module@56000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5600fe00 0x4>,
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<0x5600fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_gfx 0>;
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reset-names = "rstctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x56000000 0x1000000>;
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};
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};
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};
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@ -272,6 +272,12 @@
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>;
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};
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clkout1_pin: pinmux_clkout1_pin {
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pinctrl-single,pins = <
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0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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@ -593,6 +599,25 @@
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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ov2659@30 {
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compatible = "ovti,ov2659";
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reg = <0x30>;
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pinctrl-names = "default";
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pinctrl-0 = <&clkout1_pin>;
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clocks = <&clkout1_mux_ck>;
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clock-names = "xvclk";
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assigned-clocks = <&clkout1_mux_ck>;
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assigned-clock-parents = <&clkout1_osc_div_ck>;
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port {
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ov2659_1: endpoint {
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remote-endpoint = <&vpfe0_ep>;
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link-frequencies = /bits/ 64 <70000000>;
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};
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};
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};
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edt-ft5306@38 {
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status = "okay";
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compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
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@ -877,7 +902,7 @@
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/* Camera port */
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port {
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vpfe0_ep: endpoint {
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/* remote-endpoint = <&sensor>; add once we have it */
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remote-endpoint = <&ov2659_1>;
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ti,am437x-vpfe-interface = <0>;
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bus-width = <8>;
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hsync-active = <0>;
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@ -145,6 +145,12 @@
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system-clock-frequency = <12000000>;
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};
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};
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audio_mstrclk: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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};
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&am43xx_pinmux {
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@ -696,6 +702,21 @@
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IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
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DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
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};
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ov2659@30 {
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compatible = "ovti,ov2659";
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reg = <0x30>;
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clocks = <&audio_mstrclk>;
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clock-names = "xvclk";
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port {
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ov2659_1: endpoint {
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remote-endpoint = <&vpfe1_ep>;
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link-frequencies = /bits/ 64 <70000000>;
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};
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};
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};
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};
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&i2c2 {
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@ -962,7 +983,7 @@
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port {
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vpfe1_ep: endpoint {
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/* remote-endpoint = <&sensor>; add once we have it */
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remote-endpoint = <&ov2659_1>;
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ti,am437x-vpfe-interface = <0>;
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bus-width = <8>;
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hsync-active = <0>;
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|
|
|
@ -704,6 +704,60 @@
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ti,bit-shift = <8>;
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reg = <0x2a48>;
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};
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clkout1_osc_div_ck: clkout1-osc-div-ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sys_clkin_ck>;
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ti,bit-shift = <20>;
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ti,max-div = <4>;
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reg = <0x4100>;
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};
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clkout1_src2_mux_ck: clkout1-src2-mux-ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
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<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
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<&dpll_mpu_m2_ck>;
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reg = <0x4100>;
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};
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clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout1_src2_mux_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <8>;
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reg = <0x4100>;
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};
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clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout1_src2_pre_div_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <32>;
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ti,index-power-of-two;
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reg = <0x4100>;
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||||
};
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|
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clkout1_mux_ck: clkout1-mux-ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
|
||||
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
|
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<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
|
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ti,bit-shift = <16>;
|
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reg = <0x4100>;
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||||
};
|
||||
|
||||
clkout1_ck: clkout1-ck {
|
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#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout1_mux_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm {
|
||||
|
|
|
@ -9,6 +9,7 @@
|
|||
aliases {
|
||||
rtc0 = &tps659038_rtc;
|
||||
rtc1 = &rtc;
|
||||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
@ -96,6 +97,48 @@
|
|||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0: connector@0 {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tpd12s015_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpd12s015: encoder@0 {
|
||||
compatible = "ti,tpd12s016", "ti,tpd12s015";
|
||||
|
||||
gpios = <0>, /* optional CT_CP_HPD */
|
||||
<0>, /* optional LS_OE */
|
||||
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tpd12s015_in: endpoint@0 {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tpd12s015_out: endpoint@0 {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
|
@ -485,3 +528,19 @@
|
|||
&cpu0 {
|
||||
vdd-supply = <&smps12_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdda-supply = <&ldo4_reg>;
|
||||
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&tpd12s015_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
|
||||
*/
|
||||
|
||||
#include "omap36xx.dtsi"
|
||||
|
||||
&sgx_module {
|
||||
status = "disabled";
|
||||
};
|
|
@ -4176,35 +4176,88 @@
|
|||
};
|
||||
|
||||
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x170010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x170000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x190010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x190000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1b0000 0x4>,
|
||||
<0x1b0010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b0000 0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1d0010 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1d0000 0x10000>;
|
||||
|
||||
vpe: vpe@0 {
|
||||
compatible = "ti,dra7-vpe";
|
||||
reg = <0x0000 0x120>,
|
||||
<0x0700 0x80>,
|
||||
<0x5700 0x18>,
|
||||
<0xd000 0x400>;
|
||||
reg-names = "vpe_top",
|
||||
"sc",
|
||||
"csc",
|
||||
"vpdma";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -673,6 +673,24 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
<0x5600fe10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
};
|
||||
|
||||
crossbar_mpu: crossbar@4a002a48 {
|
||||
compatible = "ti,irq-crossbar";
|
||||
reg = <0x4a002a48 0x130>;
|
||||
|
|
|
@ -187,6 +187,12 @@
|
|||
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
|
@ -269,6 +275,23 @@
|
|||
line-name = "vin6_sel_s0";
|
||||
};
|
||||
};
|
||||
|
||||
ov5640@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
|
@ -580,3 +603,11 @@
|
|||
&pcie1_rc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -17,6 +17,48 @@
|
|||
};
|
||||
};
|
||||
|
||||
&l4_per2 {
|
||||
target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5b000 0x4>,
|
||||
<0x5b010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x5b000 0x1000>;
|
||||
|
||||
cal: cal@0 {
|
||||
compatible = "ti,dra72-cal";
|
||||
reg = <0x0000 0x400>,
|
||||
<0x0800 0x40>,
|
||||
<0x0900 0x40>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0",
|
||||
"cal_rx_core1";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,camerrx-control = <&scm_conf 0xE94>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
csi2_1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
|
|
|
@ -13,6 +13,13 @@
|
|||
model = "TI DRA762 EVM";
|
||||
compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
|
||||
|
||||
aliases {
|
||||
display0 = &hdmi0;
|
||||
|
||||
sound0 = &sound0;
|
||||
sound1 = &hdmi;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
|
@ -116,6 +123,54 @@
|
|||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tpd12s015_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpd12s015: encoder {
|
||||
compatible = "ti,tpd12s015";
|
||||
|
||||
gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
|
||||
<&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
|
||||
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tpd12s015_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tpd12s015_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
@ -317,6 +372,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ov5640@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
vdd-supply = <&buck10_reg>;
|
||||
};
|
||||
|
@ -411,6 +487,23 @@
|
|||
phy-supply = <&ldo3_reg>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
vdda_video-supply = <&ldo5_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "ok";
|
||||
|
||||
vdda-supply = <&ldo1_reg>;
|
||||
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&tpd12s015_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
spi-max-frequency = <96000000>;
|
||||
m25p80@0 {
|
||||
|
@ -447,3 +540,11 @@
|
|||
max-bitrate = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -41,6 +41,48 @@
|
|||
|
||||
};
|
||||
|
||||
&l4_per3 {
|
||||
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x1b0000 0x4>,
|
||||
<0x1b0010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>;
|
||||
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1b0000 0x10000>;
|
||||
|
||||
cal: cal@0 {
|
||||
compatible = "ti,dra76-cal";
|
||||
reg = <0x0000 0x400>,
|
||||
<0x0800 0x40>,
|
||||
<0x0900 0x40>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0",
|
||||
"cal_rx_core1";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,camerrx-control = <&scm_conf 0x6dc>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
csi2_1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* MCAN interrupts are hard-wired to irqs 67, 68 */
|
||||
&crossbar_mpu {
|
||||
ti,irqs-skip = <10 67 68 133 139 140>;
|
||||
|
|
|
@ -1591,10 +1591,10 @@
|
|||
|
||||
rtc_cm: rtc-cm@700 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x700 0x100>;
|
||||
reg = <0x700 0x60>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x700 0x100>;
|
||||
ranges = <0 0x700 0x60>;
|
||||
|
||||
rtc_clkctrl: rtc-clkctrl@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
|
@ -1603,6 +1603,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
vpe_cm: vpe-cm@760 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x760 0xc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x760 0xc>;
|
||||
|
||||
vpe_clkctrl: vpe-clkctrl@0 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x0 0xc>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&cm_core {
|
||||
|
@ -1720,6 +1734,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
cam_cm: cam-cm@1000 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x100>;
|
||||
|
||||
cam_clkctrl: cam-clkctrl@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x2c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dss_cm: dss-cm@1100 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1100 0x100>;
|
||||
|
|
|
@ -27,11 +27,12 @@
|
|||
compatible = "motorola,cpcap-battery";
|
||||
interrupts-extended = <
|
||||
&cpcap 6 0 &cpcap 5 0 &cpcap 3 0
|
||||
&cpcap 20 0 &cpcap 54 0
|
||||
&cpcap 20 0 &cpcap 54 0 &cpcap 57 0
|
||||
>;
|
||||
interrupt-names =
|
||||
"eol", "lowbph", "lowbpl",
|
||||
"chrgcurr1", "battdetb";
|
||||
"chrgcurr1", "battdetb",
|
||||
"cccal";
|
||||
io-channels = <&cpcap_adc 0 &cpcap_adc 1
|
||||
&cpcap_adc 5 &cpcap_adc 6>;
|
||||
io-channel-names = "battdetb", "battp",
|
||||
|
|
|
@ -249,6 +249,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
|
||||
&hdqw1w {
|
||||
pinctrl-0 = <&hdq_pins>;
|
||||
pinctrl-names = "default";
|
||||
ti,mode = "1w";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
tmp105@48 {
|
||||
compatible = "ti,tmp105";
|
||||
|
@ -440,6 +447,13 @@
|
|||
>;
|
||||
};
|
||||
|
||||
hdq_pins: pinmux_hdq_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* 0x4a100120 hdq_sio.hdq_sio aa27 */
|
||||
OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
/* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
|
||||
dss_hdmi_pins: pinmux_dss_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
|
@ -0,0 +1,461 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2019 André Hentschel <nerv@dawncrow.de>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "dm3725.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Amazon Echo (first generation)";
|
||||
compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0xc600000>; /* 198 MB */
|
||||
};
|
||||
|
||||
vcc5v: fixedregulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc3v3: fixedregulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc1v8: fixedregulator2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <40>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
|
||||
mute-button {
|
||||
label = "mute";
|
||||
linux,code = <KEY_MUTE>;
|
||||
gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
help-button {
|
||||
label = "help";
|
||||
linux,code = <KEY_HELP>;
|
||||
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
rotary: rotary-encoder {
|
||||
compatible = "rotary-encoder";
|
||||
gpios = <
|
||||
&gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */
|
||||
&gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */
|
||||
>;
|
||||
linux,axis = <REL_X>;
|
||||
rotary-encoder,relative-axis;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
lp5523A: lp5523A@32 {
|
||||
compatible = "national,lp5523";
|
||||
label = "q1";
|
||||
reg = <0x32>;
|
||||
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
|
||||
enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */
|
||||
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan3 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan4 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan5 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan6 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan7 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan8 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
};
|
||||
|
||||
lp5523B: lp5523B@33 {
|
||||
compatible = "national,lp5523";
|
||||
label = "q3";
|
||||
reg = <0x33>;
|
||||
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
|
||||
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan3 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan4 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan5 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan6 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan7 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan8 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
};
|
||||
|
||||
lp5523C: lp5523C@34 {
|
||||
compatible = "national,lp5523";
|
||||
label = "q4";
|
||||
reg = <0x34>;
|
||||
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
|
||||
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan3 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan4 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan5 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan6 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan7 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan8 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
};
|
||||
|
||||
lp5523D: lp552D@35 {
|
||||
compatible = "national,lp5523";
|
||||
label = "q2";
|
||||
reg = <0x35>;
|
||||
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
|
||||
|
||||
chan0 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan1 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan2 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan3 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan4 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan5 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan6 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan7 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
chan8 {
|
||||
led-cur = /bits/ 8 <12>;
|
||||
max-cur = /bits/ 8 <15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&omap3_pmx_core {
|
||||
tps_pins: pinmux_tps_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
|
||||
>;
|
||||
};
|
||||
|
||||
button_pins: pinmux_button_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
|
||||
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
|
||||
OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */
|
||||
OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */
|
||||
OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */
|
||||
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core2 {
|
||||
mmc3_pins: pinmux_mmc3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */
|
||||
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
|
||||
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc3_pins>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
vmmc-supply = <&vcc3v3>;
|
||||
vqmmc-supply = <&vcc1v8>;
|
||||
};
|
||||
|
||||
&tps {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps_pins>;
|
||||
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
ti,en-ck32k-xtal;
|
||||
ti,system-power-controller;
|
||||
|
||||
vcc1-supply = <&vcc5v>;
|
||||
vcc2-supply = <&vcc5v>;
|
||||
vcc3-supply = <&vcc5v>;
|
||||
vcc4-supply = <&vcc5v>;
|
||||
vcc5-supply = <&vcc5v>;
|
||||
vcc6-supply = <&vcc5v>;
|
||||
vcc7-supply = <&vcc5v>;
|
||||
vccio-supply = <&vcc5v>;
|
||||
|
||||
regulators {
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
regulator-name = "vdd_dsp";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = {
|
|||
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
|
||||
.wkdep_srcs = cam_wkup_sleep_deps,
|
||||
.sleepdep_srcs = cam_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain l4per_7xx_clkdm = {
|
||||
|
|
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