IB/hfi1: RSM rules for AIP
This is implementation of RSM rule for AIP packets. AIP rule will use rule RSM2 and will match standard Infiniband packet containg BTH (LNH==BTH) and having Dest QPN prefixed with value 0x81. Spread between receive contexts will be done using source QPN bits. VNIC and AIP will share receive contexts, so their rules will point to the same RMT entries and their shared code is moved to separate functions. If any of the rules is active RMT mapping will be skipped for latter. Changed function hfi1_vnic_is_rsm_full to be more general and moved it from main header to chip.c. Changed the order of RSM rules because AIP rule as more specific one is needed to be placed before more general QOS rule. Rules are occupying two last RSM registers. Link: https://lore.kernel.org/r/20200511160612.173205.73002.stgit@awfm-01.aw.intel.com Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> Signed-off-by: Kaike Wan <kaike.wan@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Grzegorz Andrejczuk
Jason Gunthorpe
Родитель
7f90a5a069
Коммит
19d8b90a50
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@ -124,13 +124,15 @@ struct flag_table {
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/*
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* RSM instance allocation
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* 0 - Verbs
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* 1 - User Fecn Handling
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* 2 - Vnic
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* 0 - User Fecn Handling
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* 1 - Vnic
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* 2 - AIP
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* 3 - Verbs
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*/
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#define RSM_INS_VERBS 0
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#define RSM_INS_FECN 1
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#define RSM_INS_VNIC 2
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#define RSM_INS_FECN 0
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#define RSM_INS_VNIC 1
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#define RSM_INS_AIP 2
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#define RSM_INS_VERBS 3
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/* Bit offset into the GUID which carries HFI id information */
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#define GUID_HFI_INDEX_SHIFT 39
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@ -171,6 +173,25 @@ struct flag_table {
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/* QPN[m+n:1] QW 1, OFFSET 1 */
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#define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
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/* RSM fields for AIP */
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/* LRH.BTH above is reused for this rule */
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/* BTH.DESTQP: QW 1, OFFSET 16 for match */
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#define BTH_DESTQP_QW 1ull
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#define BTH_DESTQP_BIT_OFFSET 16ull
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#define BTH_DESTQP_OFFSET(off) ((BTH_DESTQP_QW << QW_SHIFT) | (off))
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#define BTH_DESTQP_MATCH_OFFSET BTH_DESTQP_OFFSET(BTH_DESTQP_BIT_OFFSET)
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#define BTH_DESTQP_MASK 0xFFull
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#define BTH_DESTQP_VALUE 0x81ull
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/* DETH.SQPN: QW 1 Offset 56 for select */
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/* We use 8 most significant Soure QPN bits as entropy fpr AIP */
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#define DETH_AIP_SQPN_QW 3ull
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#define DETH_AIP_SQPN_BIT_OFFSET 56ull
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#define DETH_AIP_SQPN_OFFSET(off) ((DETH_AIP_SQPN_QW << QW_SHIFT) | (off))
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#define DETH_AIP_SQPN_SELECT_OFFSET \
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DETH_AIP_SQPN_OFFSET(DETH_AIP_SQPN_BIT_OFFSET)
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/* RSM fields for Vnic */
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/* L2_TYPE: QW 0, OFFSET 61 - for match */
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#define L2_TYPE_QW 0ull
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@ -14236,6 +14257,12 @@ static void complete_rsm_map_table(struct hfi1_devdata *dd,
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}
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}
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/* Is a receive side mapping rule */
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static bool has_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
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{
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return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0;
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}
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/*
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* Add a receive side mapping rule.
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*/
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@ -14472,39 +14499,49 @@ static void init_fecn_handling(struct hfi1_devdata *dd,
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rmt->used += total_cnt;
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}
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/* Initialize RSM for VNIC */
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void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
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static inline bool hfi1_is_rmt_full(int start, int spare)
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{
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return (start + spare) > NUM_MAP_ENTRIES;
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}
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static bool hfi1_netdev_update_rmt(struct hfi1_devdata *dd)
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{
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u8 i, j;
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u8 ctx_id = 0;
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u64 reg;
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u32 regoff;
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struct rsm_rule_data rrd;
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int rmt_start = dd->vnic.rmt_start;
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if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) {
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dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n",
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dd->vnic.rmt_start);
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return;
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/* We already have contexts mapped in RMT */
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if (has_rsm_rule(dd, RSM_INS_VNIC) || has_rsm_rule(dd, RSM_INS_AIP)) {
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dd_dev_info(dd, "Contexts are already mapped in RMT\n");
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return true;
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}
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dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n",
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dd->vnic.rmt_start,
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dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES);
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if (hfi1_is_rmt_full(rmt_start, NUM_VNIC_MAP_ENTRIES)) {
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dd_dev_err(dd, "Not enought RMT entries used = %d\n",
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rmt_start);
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return false;
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}
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dev_dbg(&(dd)->pcidev->dev, "RMT start = %d, end %d\n",
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rmt_start,
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rmt_start + NUM_VNIC_MAP_ENTRIES);
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/* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
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regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8;
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regoff = RCV_RSM_MAP_TABLE + (rmt_start / 8) * 8;
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reg = read_csr(dd, regoff);
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for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) {
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/* Update map register with vnic context */
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j = (dd->vnic.rmt_start + i) % 8;
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/* Update map register with netdev context */
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j = (rmt_start + i) % 8;
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reg &= ~(0xffllu << (j * 8));
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reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8);
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/* Wrap up vnic ctx index */
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/* Wrap up netdev ctx index */
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ctx_id %= dd->vnic.num_ctxt;
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/* Write back map register */
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if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) {
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dev_dbg(&(dd)->pcidev->dev,
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"Vnic rsm map reg[%d] =0x%llx\n",
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"RMT[%d] =0x%llx\n",
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regoff - RCV_RSM_MAP_TABLE, reg);
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write_csr(dd, regoff, reg);
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@ -14514,35 +14551,83 @@ void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
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}
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}
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/* Add rule for vnic */
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rrd.offset = dd->vnic.rmt_start;
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rrd.pkt_type = 4;
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/* Match 16B packets */
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rrd.field1_off = L2_TYPE_MATCH_OFFSET;
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rrd.mask1 = L2_TYPE_MASK;
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rrd.value1 = L2_16B_VALUE;
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/* Match ETH L4 packets */
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rrd.field2_off = L4_TYPE_MATCH_OFFSET;
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rrd.mask2 = L4_16B_TYPE_MASK;
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rrd.value2 = L4_16B_ETH_VALUE;
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/* Calc context from veswid and entropy */
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rrd.index1_off = L4_16B_HDR_VESWID_OFFSET;
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rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES);
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rrd.index2_off = L2_16B_ENTROPY_OFFSET;
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rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES);
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add_rsm_rule(dd, RSM_INS_VNIC, &rrd);
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return true;
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}
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/* Enable RSM if not already enabled */
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static void hfi1_enable_rsm_rule(struct hfi1_devdata *dd,
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int rule, struct rsm_rule_data *rrd)
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{
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if (!hfi1_netdev_update_rmt(dd)) {
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dd_dev_err(dd, "Failed to update RMT for RSM%d rule\n", rule);
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return;
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}
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add_rsm_rule(dd, rule, rrd);
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add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
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}
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void hfi1_init_aip_rsm(struct hfi1_devdata *dd)
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{
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/*
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* go through with the initialisation only if this rule actually doesn't
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* exist yet
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*/
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if (atomic_fetch_inc(&dd->ipoib_rsm_usr_num) == 0) {
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struct rsm_rule_data rrd = {
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.offset = dd->vnic.rmt_start,
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.pkt_type = IB_PACKET_TYPE,
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.field1_off = LRH_BTH_MATCH_OFFSET,
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.mask1 = LRH_BTH_MASK,
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.value1 = LRH_BTH_VALUE,
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.field2_off = BTH_DESTQP_MATCH_OFFSET,
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.mask2 = BTH_DESTQP_MASK,
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.value2 = BTH_DESTQP_VALUE,
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.index1_off = DETH_AIP_SQPN_SELECT_OFFSET +
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ilog2(NUM_VNIC_MAP_ENTRIES),
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.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES),
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.index2_off = DETH_AIP_SQPN_SELECT_OFFSET,
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.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES)
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};
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hfi1_enable_rsm_rule(dd, RSM_INS_AIP, &rrd);
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}
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}
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/* Initialize RSM for VNIC */
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void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
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{
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struct rsm_rule_data rrd = {
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/* Add rule for vnic */
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.offset = dd->vnic.rmt_start,
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.pkt_type = 4,
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/* Match 16B packets */
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.field1_off = L2_TYPE_MATCH_OFFSET,
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.mask1 = L2_TYPE_MASK,
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.value1 = L2_16B_VALUE,
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/* Match ETH L4 packets */
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.field2_off = L4_TYPE_MATCH_OFFSET,
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.mask2 = L4_16B_TYPE_MASK,
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.value2 = L4_16B_ETH_VALUE,
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/* Calc context from veswid and entropy */
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.index1_off = L4_16B_HDR_VESWID_OFFSET,
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.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES),
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.index2_off = L2_16B_ENTROPY_OFFSET,
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.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES)
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};
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hfi1_enable_rsm_rule(dd, RSM_INS_VNIC, &rrd);
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}
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void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd)
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{
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clear_rsm_rule(dd, RSM_INS_VNIC);
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}
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/* Disable RSM if used only by vnic */
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if (dd->vnic.rmt_start == 0)
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clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
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void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd)
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{
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/* only actually clear the rule if it's the last user asking to do so */
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if (atomic_fetch_add_unless(&dd->ipoib_rsm_usr_num, -1, 0) == 1)
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clear_rsm_rule(dd, RSM_INS_AIP);
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}
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static int init_rxe(struct hfi1_devdata *dd)
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@ -1,7 +1,7 @@
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#ifndef _CHIP_H
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#define _CHIP_H
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/*
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* Copyright(c) 2015 - 2018 Intel Corporation.
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* Copyright(c) 2015 - 2020 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -1455,6 +1455,8 @@ void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr);
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void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr);
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void reset_interrupts(struct hfi1_devdata *dd);
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u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx);
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void hfi1_init_aip_rsm(struct hfi1_devdata *dd);
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void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd);
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/*
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* Interrupt source table.
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@ -1417,12 +1417,10 @@ struct hfi1_devdata {
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struct hfi1_vnic_data vnic;
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/* Lock to protect IRQ SRC register access */
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spinlock_t irq_src_lock;
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};
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static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
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{
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return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
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}
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/* Keeps track of IPoIB RSM rule users */
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atomic_t ipoib_rsm_usr_num;
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};
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/* 8051 firmware version helper */
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#define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2015 - 2018 Intel Corporation.
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* Copyright(c) 2015 - 2020 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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@ -1316,6 +1316,7 @@ static struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev,
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goto bail;
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}
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atomic_set(&dd->ipoib_rsm_usr_num, 0);
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return dd;
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bail:
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