crypto: octeontx2 - add virtual function driver support
Add support for the Marvell OcteonTX2 CPT virtual function driver. This patch includes probe, PCI specific initialization and interrupt handling. Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Srujana Challa
Herbert Xu
Родитель
78506c2a1e
Коммит
19d8e8c7be
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@ -1,7 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o
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obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o octeontx2-cptvf.o
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octeontx2-cpt-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \
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otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o
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octeontx2-cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \
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otx2_cpt_mbox_common.o
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ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af
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@ -115,5 +115,6 @@ int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
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struct otx2_cptlfs_info;
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int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
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#endif /* __OTX2_CPT_COMMON_H */
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@ -168,3 +168,35 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)
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return ret;
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}
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int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs)
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{
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struct otx2_mbox *mbox = lfs->mbox;
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struct pci_dev *pdev = lfs->pdev;
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struct mbox_msghdr *req;
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int ret, i;
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req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
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sizeof(struct msix_offset_rsp));
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if (req == NULL) {
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dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
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return -EFAULT;
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}
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req->id = MBOX_MSG_MSIX_OFFSET;
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req->sig = OTX2_MBOX_REQ_SIG;
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req->pcifunc = 0;
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ret = otx2_cpt_send_mbox_msg(mbox, pdev);
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if (ret)
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return ret;
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for (i = 0; i < lfs->lfs_num; i++) {
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if (lfs->lf[i].msix_offset == MSIX_VECTOR_INVALID) {
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dev_err(&pdev->dev,
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"Invalid msix offset %d for LF %d\n",
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lfs->lf[i].msix_offset, i);
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return -EINVAL;
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}
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}
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return ret;
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}
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __OTX2_CPTVF_H
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#define __OTX2_CPTVF_H
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#include "mbox.h"
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#include "otx2_cptlf.h"
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struct otx2_cptvf_dev {
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void __iomem *reg_base; /* Register start address */
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void __iomem *pfvf_mbox_base; /* PF-VF mbox start address */
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struct pci_dev *pdev; /* PCI device handle */
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struct otx2_cptlfs_info lfs; /* CPT LFs attached to this VF */
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u8 vf_id; /* Virtual function index */
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/* PF <=> VF mbox */
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struct otx2_mbox pfvf_mbox;
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struct work_struct pfvf_mbox_work;
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struct workqueue_struct *pfvf_mbox_wq;
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};
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irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);
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void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work);
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int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);
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#endif /* __OTX2_CPTVF_H */
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@ -0,0 +1,196 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2020 Marvell. */
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#include "otx2_cpt_common.h"
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#include "otx2_cptvf.h"
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#include <rvu_reg.h>
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#define OTX2_CPTVF_DRV_NAME "octeontx2-cptvf"
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static void cptvf_enable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
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{
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/* Clear interrupt if any */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
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0x1ULL);
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/* Enable PF-VF interrupt */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT_ENA_W1S, 0x1ULL);
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}
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static void cptvf_disable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
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{
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/* Disable PF-VF interrupt */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT_ENA_W1C, 0x1ULL);
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/* Clear interrupt if any */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
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0x1ULL);
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}
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static int cptvf_register_interrupts(struct otx2_cptvf_dev *cptvf)
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{
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int ret, irq;
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u32 num_vec;
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num_vec = pci_msix_vec_count(cptvf->pdev);
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if (num_vec <= 0)
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return -EINVAL;
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/* Enable MSI-X */
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ret = pci_alloc_irq_vectors(cptvf->pdev, num_vec, num_vec,
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PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_err(&cptvf->pdev->dev,
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"Request for %d msix vectors failed\n", num_vec);
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return ret;
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}
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irq = pci_irq_vector(cptvf->pdev, OTX2_CPT_VF_INT_VEC_E_MBOX);
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/* Register VF<=>PF mailbox interrupt handler */
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ret = devm_request_irq(&cptvf->pdev->dev, irq,
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otx2_cptvf_pfvf_mbox_intr, 0,
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"CPTPFVF Mbox", cptvf);
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if (ret)
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return ret;
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/* Enable PF-VF mailbox interrupts */
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cptvf_enable_pfvf_mbox_intrs(cptvf);
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ret = otx2_cpt_send_ready_msg(&cptvf->pfvf_mbox, cptvf->pdev);
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if (ret) {
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dev_warn(&cptvf->pdev->dev,
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"PF not responding to mailbox, deferring probe\n");
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cptvf_disable_pfvf_mbox_intrs(cptvf);
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return -EPROBE_DEFER;
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}
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return 0;
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}
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static int cptvf_pfvf_mbox_init(struct otx2_cptvf_dev *cptvf)
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{
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int ret;
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cptvf->pfvf_mbox_wq = alloc_workqueue("cpt_pfvf_mailbox",
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WQ_UNBOUND | WQ_HIGHPRI |
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WQ_MEM_RECLAIM, 1);
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if (!cptvf->pfvf_mbox_wq)
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return -ENOMEM;
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ret = otx2_mbox_init(&cptvf->pfvf_mbox, cptvf->pfvf_mbox_base,
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cptvf->pdev, cptvf->reg_base, MBOX_DIR_VFPF, 1);
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if (ret)
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goto free_wqe;
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INIT_WORK(&cptvf->pfvf_mbox_work, otx2_cptvf_pfvf_mbox_handler);
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return 0;
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free_wqe:
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destroy_workqueue(cptvf->pfvf_mbox_wq);
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return ret;
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}
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static void cptvf_pfvf_mbox_destroy(struct otx2_cptvf_dev *cptvf)
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{
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destroy_workqueue(cptvf->pfvf_mbox_wq);
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otx2_mbox_destroy(&cptvf->pfvf_mbox);
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}
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static int otx2_cptvf_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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resource_size_t offset, size;
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struct otx2_cptvf_dev *cptvf;
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int ret;
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cptvf = devm_kzalloc(dev, sizeof(*cptvf), GFP_KERNEL);
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if (!cptvf)
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return -ENOMEM;
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(dev, "Failed to enable PCI device\n");
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goto clear_drvdata;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
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if (ret) {
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dev_err(dev, "Unable to get usable DMA configuration\n");
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goto clear_drvdata;
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}
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/* Map VF's configuration registers */
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ret = pcim_iomap_regions_request_all(pdev, 1 << PCI_PF_REG_BAR_NUM,
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OTX2_CPTVF_DRV_NAME);
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if (ret) {
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dev_err(dev, "Couldn't get PCI resources 0x%x\n", ret);
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goto clear_drvdata;
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}
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pci_set_master(pdev);
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pci_set_drvdata(pdev, cptvf);
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cptvf->pdev = pdev;
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cptvf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
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offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
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size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
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/* Map PF-VF mailbox memory */
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cptvf->pfvf_mbox_base = devm_ioremap_wc(dev, offset, size);
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if (!cptvf->pfvf_mbox_base) {
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dev_err(&pdev->dev, "Unable to map BAR4\n");
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ret = -ENODEV;
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goto clear_drvdata;
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}
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/* Initialize PF<=>VF mailbox */
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ret = cptvf_pfvf_mbox_init(cptvf);
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if (ret)
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goto clear_drvdata;
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/* Register interrupts */
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ret = cptvf_register_interrupts(cptvf);
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if (ret)
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goto destroy_pfvf_mbox;
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return 0;
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destroy_pfvf_mbox:
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cptvf_pfvf_mbox_destroy(cptvf);
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clear_drvdata:
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pci_set_drvdata(pdev, NULL);
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return ret;
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}
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static void otx2_cptvf_remove(struct pci_dev *pdev)
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{
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struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
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if (!cptvf) {
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dev_err(&pdev->dev, "Invalid CPT VF device.\n");
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return;
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}
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/* Disable PF-VF mailbox interrupt */
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cptvf_disable_pfvf_mbox_intrs(cptvf);
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/* Destroy PF-VF mbox */
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cptvf_pfvf_mbox_destroy(cptvf);
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pci_set_drvdata(pdev, NULL);
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}
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/* Supported devices */
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static const struct pci_device_id otx2_cptvf_id_table[] = {
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{PCI_VDEVICE(CAVIUM, OTX2_CPT_PCI_VF_DEVICE_ID), 0},
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{ 0, } /* end of table */
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};
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static struct pci_driver otx2_cptvf_pci_driver = {
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.name = OTX2_CPTVF_DRV_NAME,
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.id_table = otx2_cptvf_id_table,
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.probe = otx2_cptvf_probe,
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.remove = otx2_cptvf_remove,
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};
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module_pci_driver(otx2_cptvf_pci_driver);
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MODULE_AUTHOR("Marvell");
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MODULE_DESCRIPTION("Marvell OcteonTX2 CPT Virtual Function Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_DEVICE_TABLE(pci, otx2_cptvf_id_table);
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@ -0,0 +1,113 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2020 Marvell. */
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#include "otx2_cpt_common.h"
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#include "otx2_cptvf.h"
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#include <rvu_reg.h>
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irqreturn_t otx2_cptvf_pfvf_mbox_intr(int __always_unused irq, void *arg)
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{
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struct otx2_cptvf_dev *cptvf = arg;
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u64 intr;
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/* Read the interrupt bits */
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intr = otx2_cpt_read64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT);
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if (intr & 0x1ULL) {
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/* Schedule work queue function to process the MBOX request */
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queue_work(cptvf->pfvf_mbox_wq, &cptvf->pfvf_mbox_work);
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/* Clear and ack the interrupt */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT, 0x1ULL);
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}
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return IRQ_HANDLED;
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}
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static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,
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struct mbox_msghdr *msg)
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{
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struct otx2_cptlfs_info *lfs = &cptvf->lfs;
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struct cpt_rd_wr_reg_msg *rsp_reg;
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struct msix_offset_rsp *rsp_msix;
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int i;
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if (msg->id >= MBOX_MSG_MAX) {
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dev_err(&cptvf->pdev->dev,
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"MBOX msg with unknown ID %d\n", msg->id);
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return;
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}
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if (msg->sig != OTX2_MBOX_RSP_SIG) {
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dev_err(&cptvf->pdev->dev,
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"MBOX msg with wrong signature %x, ID %d\n",
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msg->sig, msg->id);
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return;
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}
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switch (msg->id) {
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case MBOX_MSG_READY:
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cptvf->vf_id = ((msg->pcifunc >> RVU_PFVF_FUNC_SHIFT)
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& RVU_PFVF_FUNC_MASK) - 1;
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break;
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case MBOX_MSG_ATTACH_RESOURCES:
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/* Check if resources were successfully attached */
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if (!msg->rc)
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lfs->are_lfs_attached = 1;
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break;
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case MBOX_MSG_DETACH_RESOURCES:
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/* Check if resources were successfully detached */
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if (!msg->rc)
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lfs->are_lfs_attached = 0;
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break;
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case MBOX_MSG_MSIX_OFFSET:
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rsp_msix = (struct msix_offset_rsp *) msg;
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for (i = 0; i < rsp_msix->cptlfs; i++)
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lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i];
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break;
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case MBOX_MSG_CPT_RD_WR_REGISTER:
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rsp_reg = (struct cpt_rd_wr_reg_msg *) msg;
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if (msg->rc) {
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dev_err(&cptvf->pdev->dev,
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"Reg %llx rd/wr(%d) failed %d\n",
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rsp_reg->reg_offset, rsp_reg->is_write,
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msg->rc);
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return;
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}
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if (!rsp_reg->is_write)
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*rsp_reg->ret_val = rsp_reg->val;
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break;
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default:
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dev_err(&cptvf->pdev->dev, "Unsupported msg %d received.\n",
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msg->id);
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break;
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}
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}
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void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work)
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{
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struct otx2_cptvf_dev *cptvf;
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struct otx2_mbox *pfvf_mbox;
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struct otx2_mbox_dev *mdev;
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struct mbox_hdr *rsp_hdr;
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struct mbox_msghdr *msg;
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int offset, i;
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/* sync with mbox memory region */
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smp_rmb();
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cptvf = container_of(work, struct otx2_cptvf_dev, pfvf_mbox_work);
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pfvf_mbox = &cptvf->pfvf_mbox;
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mdev = &pfvf_mbox->dev[0];
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rsp_hdr = (struct mbox_hdr *)(mdev->mbase + pfvf_mbox->rx_start);
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if (rsp_hdr->num_msgs == 0)
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return;
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offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < rsp_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)(mdev->mbase + pfvf_mbox->rx_start +
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offset);
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process_pfvf_mbox_mbox_msg(cptvf, msg);
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offset = msg->next_msgoff;
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mdev->msgs_acked++;
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}
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otx2_mbox_reset(pfvf_mbox, 0);
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}
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