phy: for 5.6-rc
*) Fix phy_get() from erroring out if device link creation failed *) Fix write timeouts in Motorola Mapphone mdm6600 PHY *) Fix Broadcom brcm-sata PHY driver to write to the correct MDIO register *) Add GMII PHY mode in supported modes of TI AM335x/437x/5xx SoCs Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEUXMr/TfP2p4suIY5Dlx4XIBNgtkFAl5fkMgOHGtpc2hvbkB0 aS5jb20ACgkQDlx4XIBNgtmBdw/+KxOnAglcOtf3ufgumDhpg0AM7okViCPnd4YS w7IRcIcZIAwRjXOfsvdPtQrymmjlWhEfeh/e+A232I2VAn4oUpm4sItil9O8lNq6 5j5343ZwhIu1fom1ORashiRTOrdY9H1e1LfJhiIzIrYtw2eeIGLanz11l/5vzVZ4 3ZHbrfYSgYqlv0p/A23IOQirdJ4heLNDMln2d8RANJI/yr/jDGYruDvyxX5DMYQj m848xDMZLLOHk0ihNzmXX6pfCAmYig/FHBzM8O1GS+1Wfcje03l9nSG5b7zb0bre x9PKFnRgPY6t5SRuDDkSZZdSPe2inuG0TSoMnateN94QBL/r+Ky70TDV7cohLqSu wN5MlQ5sgQ6mU76tpUwyscgDzTMGcEtvmRVhCVbm1Z2HRSNJ5J4RY8ebvc9HQAdV UfxdbgaVSEna2qiluxlr8PyyU2Mlr+xjgvkLzQeKlfF2JbTGM+03H/XYkJvctpE0 P8RlbjHgicRICROQ/+KHIB6iyRJJFE/SOYUI7pB4fI7pbyfYJ6aRJms9BTCjpeuD KMmrB4z3e0x/iczTEk2cYJ/Zc9dI0PLHwFsrbKBOvV6msZWPLqJKNu8nOBGRZkVt 0H+uD6BObzaK5Mrk058yFUwL9UezfkHks1h5wYcsuXEzpy2WDUQAKPlq3amVJNe8 y2IVP/Y= =iSMT -----END PGP SIGNATURE----- Merge tag 'phy-for-5.6-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-linus Kishon writes: phy: for 5.6-rc *) Fix phy_get() from erroring out if device link creation failed *) Fix write timeouts in Motorola Mapphone mdm6600 PHY *) Fix Broadcom brcm-sata PHY driver to write to the correct MDIO register *) Add GMII PHY mode in supported modes of TI AM335x/437x/5xx SoCs Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.6-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: mapphone-mdm6600: Fix timeouts by adding wake-up handling phy: brcm-sata: Correct MDIO operations for 40nm platforms phy: ti: gmii-sel: do not fail in case of gmii phy: ti: gmii-sel: fix set of copy-paste errors phy: core: Fix phy_get() to not return error on link creation failure phy: mapphone-mdm6600: Fix write timeouts with shorter GPIO toggle interval
This commit is contained in:
Greg Kroah-Hartman
Коммит
19f3c1e98b
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@ -186,29 +186,6 @@ enum sata_phy_ctrl_regs {
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PHY_CTRL_1_RESET = BIT(0),
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};
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static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 size = 0;
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switch (priv->version) {
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case BRCM_SATA_PHY_STB_16NM:
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_IPROC_NS2:
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case BRCM_SATA_PHY_DSL_28NM:
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size = SATA_PCB_REG_28NM_SPACE_SIZE;
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break;
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case BRCM_SATA_PHY_STB_40NM:
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size = SATA_PCB_REG_40NM_SPACE_SIZE;
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break;
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default:
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dev_err(priv->dev, "invalid phy version\n");
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break;
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}
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return priv->phy_base + (port->portnum * size);
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}
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static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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@ -226,19 +203,34 @@ static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
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return priv->ctrl_base + (port->portnum * size);
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}
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static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
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static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
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u32 ofs, u32 msk, u32 value)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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void __iomem *pcb_base = priv->phy_base;
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u32 tmp;
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if (priv->version == BRCM_SATA_PHY_STB_40NM)
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bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
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else
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pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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tmp = (tmp & msk) | value;
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writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
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static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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void __iomem *pcb_base = priv->phy_base;
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if (priv->version == BRCM_SATA_PHY_STB_40NM)
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bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
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else
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pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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@ -250,16 +242,15 @@ static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
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static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_pcb_base(port);
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 tmp;
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/* override the TX spread spectrum setting */
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tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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/* set fixed min freq */
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
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STB_FMIN_VAL_DEFAULT);
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@ -271,7 +262,7 @@ static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
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tmp = STB_FMAX_VAL_DEFAULT;
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}
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
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}
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@ -280,7 +271,6 @@ static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
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static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_pcb_base(port);
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u32 tmp = 0, reg = 0;
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switch (port->rxaeq_mode) {
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@ -301,8 +291,8 @@ static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
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break;
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}
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brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
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brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
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brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
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brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
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return 0;
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}
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@ -316,18 +306,17 @@ static int brcm_stb_sata_init(struct brcm_sata_port *port)
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static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_pcb_base(port);
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u32 tmp, value;
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/* Reduce CP tail current to 1/16th of its default value */
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
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brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
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/* Turn off CP tail current boost */
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
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brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
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/* Set a specific AEQ equalizer value */
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tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
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brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
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brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
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~(tmp | AEQ_RFZ_FRC_VAL |
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AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
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tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
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@ -337,7 +326,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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value = 0x52;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
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brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
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~RXPMD_RX_PPM_VAL_MASK, value);
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/* Set proportional loop bandwith Gen1/2/3 */
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@ -352,7 +341,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
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1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
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1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
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brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
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value);
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/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
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@ -365,7 +354,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
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brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
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~tmp, value);
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/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
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@ -378,7 +367,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
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brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
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~tmp, value);
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/* Set no guard band and clamp CDR */
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@ -387,11 +376,11 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
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value = 0x51;
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else
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value = 0;
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brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
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brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
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~tmp, RXPMD_MON_CORRECT_EN | value);
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/* Turn on/off SSC */
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brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
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brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
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port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
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return 0;
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@ -411,7 +400,6 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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{
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int try;
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unsigned int val;
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void __iomem *base = brcm_sata_pcb_base(port);
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void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
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struct device *dev = port->phy_priv->dev;
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@ -421,24 +409,24 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
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val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
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val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
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brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
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val = 0x0;
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val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
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val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
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val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
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brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
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/* Configure PHY PLL register bank 1 */
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val = NS2_PLL1_ACTRL2_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
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brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
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val = NS2_PLL1_ACTRL3_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
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brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
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val = NS2_PLL1_ACTRL4_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
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brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
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/* Configure PHY BLOCK0 register bank */
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/* Set oob_clk_sel to refclk/2 */
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brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
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brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
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~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
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BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
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@ -451,7 +439,7 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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/* Wait for PHY PLL lock by polling pll_lock bit */
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try = 50;
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while (try) {
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val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
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val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
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BLOCK0_XGXSSTATUS);
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if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
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break;
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@ -471,9 +459,7 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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static int brcm_nsp_sata_init(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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struct device *dev = port->phy_priv->dev;
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void __iomem *base = priv->phy_base;
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unsigned int oob_bank;
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unsigned int val, try;
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@ -490,36 +476,36 @@ static int brcm_nsp_sata_init(struct brcm_sata_port *port)
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val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
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val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
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val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
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brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
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val = 0x0;
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val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
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val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
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val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
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brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
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brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
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~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
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0x0c << PLL_ACTRL2_SELDIV_SHIFT);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
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brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
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0xff0, 0x4f0);
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val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, val);
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val = PLLCONTROL_0_SEQ_START;
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, 0);
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mdelay(10);
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brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
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~val, val);
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|
||||
/* Wait for pll_seq_done bit */
|
||||
try = 50;
|
||||
while (--try) {
|
||||
val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -546,27 +532,25 @@ static int brcm_nsp_sata_init(struct brcm_sata_port *port)
|
|||
|
||||
static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
void __iomem *base = priv->phy_base;
|
||||
unsigned int val, try;
|
||||
|
||||
/* Configure PHY PLL register bank 1 */
|
||||
val = SR_PLL1_ACTRL2_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
val = SR_PLL1_ACTRL3_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
val = SR_PLL1_ACTRL4_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
|
||||
/* Configure PHY PLL register bank 0 */
|
||||
val = SR_PLL0_ACTRL6_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
|
||||
|
||||
/* Wait for PHY PLL lock by polling pll_lock bit */
|
||||
try = 50;
|
||||
do {
|
||||
val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -581,7 +565,7 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
|||
}
|
||||
|
||||
/* Invert Tx polarity */
|
||||
brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
|
||||
brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
|
||||
~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
|
||||
|
||||
/* Configure OOB control to handle 100MHz reference clock */
|
||||
|
|
@ -589,52 +573,51 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
|||
(0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
|
||||
(0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
|
||||
(0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
|
||||
(0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
|
||||
(0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcm_dsl_sata_init(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
unsigned int try;
|
||||
u32 tmp;
|
||||
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
0, 0x3089);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
0, 0x3088);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
|
||||
0, 0x3000);
|
||||
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
|
||||
0, 0x3000);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
/* Acquire PLL lock */
|
||||
try = 50;
|
||||
while (try) {
|
||||
tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -687,10 +670,9 @@ static int brcm_sata_phy_init(struct phy *phy)
|
|||
|
||||
static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
u32 tmp = BIT(8);
|
||||
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
~tmp, tmp);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
|
||||
#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */
|
||||
#define PHY_MDM6600_WAKE_KICK_MS 600 /* time on after GPIO toggle */
|
||||
#define MDM6600_MODEM_IDLE_DELAY_MS 1000 /* modem after USB suspend */
|
||||
#define MDM6600_MODEM_WAKE_DELAY_MS 200 /* modem response after idle */
|
||||
|
||||
|
|
@ -243,10 +244,24 @@ static irqreturn_t phy_mdm6600_wakeirq_thread(int irq, void *data)
|
|||
{
|
||||
struct phy_mdm6600 *ddata = data;
|
||||
struct gpio_desc *mode_gpio1;
|
||||
int error, wakeup;
|
||||
|
||||
mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1];
|
||||
dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n",
|
||||
gpiod_get_value(mode_gpio1));
|
||||
wakeup = gpiod_get_value(mode_gpio1);
|
||||
if (!wakeup)
|
||||
return IRQ_NONE;
|
||||
|
||||
dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n", wakeup);
|
||||
error = pm_runtime_get_sync(ddata->dev);
|
||||
if (error < 0) {
|
||||
pm_runtime_put_noidle(ddata->dev);
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/* Just wake-up and kick the autosuspend timer */
|
||||
pm_runtime_mark_last_busy(ddata->dev);
|
||||
pm_runtime_put_autosuspend(ddata->dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
@ -496,8 +511,14 @@ static void phy_mdm6600_modem_wake(struct work_struct *work)
|
|||
|
||||
ddata = container_of(work, struct phy_mdm6600, modem_wake_work.work);
|
||||
phy_mdm6600_wake_modem(ddata);
|
||||
|
||||
/*
|
||||
* The modem does not always stay awake 1.2 seconds after toggling
|
||||
* the wake GPIO, and sometimes it idles after about some 600 ms
|
||||
* making writes time out.
|
||||
*/
|
||||
schedule_delayed_work(&ddata->modem_wake_work,
|
||||
msecs_to_jiffies(MDM6600_MODEM_IDLE_DELAY_MS));
|
||||
msecs_to_jiffies(PHY_MDM6600_WAKE_KICK_MS));
|
||||
}
|
||||
|
||||
static int __maybe_unused phy_mdm6600_runtime_suspend(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -688,11 +688,9 @@ struct phy *phy_get(struct device *dev, const char *string)
|
|||
get_device(&phy->dev);
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
@ -803,11 +801,9 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
|
|||
}
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
@ -852,11 +848,9 @@ struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np,
|
|||
devres_add(dev, ptr);
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -80,20 +80,20 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
|
|||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
mode = AM33XX_GMII_SEL_MODE_MII;
|
||||
case PHY_INTERFACE_MODE_GMII:
|
||||
gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_warn(dev,
|
||||
"port%u: unsupported mode: \"%s\". Defaulting to MII.\n",
|
||||
if_phy->id, phy_modes(rgmii_id));
|
||||
dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
|
||||
if_phy->id, phy_modes(submode));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if_phy->phy_if_mode = submode;
|
||||
|
||||
dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
|
||||
__func__, if_phy->id, mode, rgmii_id,
|
||||
__func__, if_phy->id, submode, rgmii_id,
|
||||
if_phy->rmii_clock_external);
|
||||
|
||||
regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
|
||||
|
|
|
|||
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