clk: oxnas: Rename to clk_oxnas_gate
Rename clock ops to clk_oxnas_gate in ops and structures. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-4-narmstrong@baylibre.com
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@ -26,7 +26,7 @@
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#include <linux/mfd/syscon.h>
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/* Standard regmap gate clocks */
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struct clk_oxnas {
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struct clk_oxnas_gate {
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struct clk_hw hw;
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signed char bit;
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struct regmap *regmap;
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@ -37,14 +37,14 @@ struct clk_oxnas {
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#define CLK_SET_REGOFFSET 0x2c
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#define CLK_CLR_REGOFFSET 0x30
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static inline struct clk_oxnas *to_clk_oxnas(struct clk_hw *hw)
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static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_oxnas, hw);
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return container_of(hw, struct clk_oxnas_gate, hw);
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}
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static int oxnas_clk_is_enabled(struct clk_hw *hw)
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static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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int ret;
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unsigned int val;
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@ -55,26 +55,26 @@ static int oxnas_clk_is_enabled(struct clk_hw *hw)
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return val & BIT(std->bit);
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}
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static int oxnas_clk_enable(struct clk_hw *hw)
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static int oxnas_clk_gate_enable(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
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return 0;
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}
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static void oxnas_clk_disable(struct clk_hw *hw)
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static void oxnas_clk_gate_disable(struct clk_hw *hw)
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{
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struct clk_oxnas *std = to_clk_oxnas(hw);
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
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}
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static const struct clk_ops oxnas_clk_ops = {
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.enable = oxnas_clk_enable,
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.disable = oxnas_clk_disable,
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.is_enabled = oxnas_clk_is_enabled,
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static const struct clk_ops oxnas_clk_gate_ops = {
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.enable = oxnas_clk_gate_enable,
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.disable = oxnas_clk_gate_disable,
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.is_enabled = oxnas_clk_gate_is_enabled,
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};
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static const char *const oxnas_clk_parents[] = {
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@ -88,7 +88,7 @@ static const char *const eth_parents[] = {
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#define DECLARE_STD_CLKP(__clk, __parent) \
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static const struct clk_init_data clk_##__clk##_init = { \
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.name = __stringify(__clk), \
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.ops = &oxnas_clk_ops, \
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.ops = &oxnas_clk_gate_ops, \
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.parent_names = __parent, \
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.num_parents = ARRAY_SIZE(__parent), \
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}
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@ -127,7 +127,7 @@ static const struct clk_oxnas_init_data clk_oxnas_init[] = {
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};
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struct clk_oxnas_data {
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struct clk_oxnas clk_oxnas[ARRAY_SIZE(clk_oxnas_init)];
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struct clk_oxnas_gate clk_oxnas[ARRAY_SIZE(clk_oxnas_init)];
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struct clk_onecell_data onecell_data[ARRAY_SIZE(clk_oxnas_init)];
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struct clk *clks[ARRAY_SIZE(clk_oxnas_init)];
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};
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@ -150,7 +150,7 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
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}
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for (i = 0; i < ARRAY_SIZE(clk_oxnas_init); i++) {
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struct clk_oxnas *_clk;
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struct clk_oxnas_gate *_clk;
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_clk = &clk_oxnas->clk_oxnas[i];
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_clk->bit = clk_oxnas_init[i].bit;
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