drm/radeon/kms: DP fixes and cleanup from the ddx
- dpcp -> dpcd - fix up dig encoder routing - aux transaction table takes delay in 10 usec units Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
Родитель
746c1aa4d1
Коммит
1a66c95a64
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@ -34,7 +34,7 @@
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#define DP_LINK_STATUS_SIZE 6
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bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
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int num_bytes, u8 *read_byte,
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int num_bytes, u8 *read_byte,
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u8 read_buf_len, u8 delay)
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{
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struct drm_device *dev = chan->dev;
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@ -42,9 +42,9 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
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PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
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unsigned char *base;
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memset(&args, 0, sizeof(args));
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base = (unsigned char *)rdev->mode_info.atom_context->scratch;
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memcpy(base, req_bytes, num_bytes);
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@ -53,7 +53,7 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
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args.lpDataOut = 16;
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args.ucDataOutLen = 0;
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args.ucChannelID = chan->i2c_id;
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args.ucDelay = delay;
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args.ucDelay = delay / 10;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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@ -158,24 +158,24 @@ bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16
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return ret;
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}
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void radeon_dp_getdpcp(struct radeon_connector *radeon_connector)
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void radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
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{
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struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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u8 msg[25];
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int ret;
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ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCP_REV, 0, 8, msg);
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ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
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if (ret) {
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memcpy(radeon_dig_connector->dpcp, msg, 8);
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{
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memcpy(radeon_dig_connector->dpcd, msg, 8);
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{
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int i;
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printk("DPCP: ");
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printk("DPCD: ");
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for (i = 0; i < 8; i++)
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printk("%02x ", msg[i]);
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printk("\n");
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}
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}
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radeon_dig_connector->dpcp[0] = 0;
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radeon_dig_connector->dpcd[0] = 0;
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return;
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}
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@ -199,8 +199,8 @@ static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
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static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
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{
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struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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if (radeon_dig_connector->dpcp[0] >= 0x11) {
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radeon_dp_aux_native_write(radeon_connector, 0x600, 1,
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if (radeon_dig_connector->dpcd[0] >= 0x11) {
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radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
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&power_state);
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}
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}
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@ -923,7 +923,7 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
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sink_type = radeon_dp_getsinktype(radeon_connector);
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if (sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
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radeon_dp_getdpcp(radeon_connector);
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radeon_dp_getdpcd(radeon_connector);
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ret = connector_status_connected;
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}
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return ret;
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@ -605,6 +605,30 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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}
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}
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/*
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* DIG Encoder/Transmitter Setup
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*
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* DCE 3.0/3.1
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* - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
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* Supports up to 3 digital outputs
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* - 2 DIG encoder blocks.
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* DIG1 can drive UNIPHY link A or link B
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* DIG2 can drive UNIPHY link B or LVTMA
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*
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* DCE 3.2
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* - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
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* Supports up to 5 digital outputs
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* - 2 DIG encoder blocks.
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* DIG1/2 can drive UNIPHY0/1/2 link A or link B
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*
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* Routing
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* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
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* Examples:
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* crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
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* crtc1 -> dig1 -> UNIPHY0 link B -> DP
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* crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
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* crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
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*/
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static void
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atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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{
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@ -646,10 +670,17 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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} else {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
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/* XXX doesn't really matter which dig encoder we pick as long as it's
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* not already in use
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*/
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if (dig_connector->linkb)
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index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
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else
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index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
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num = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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/* Only dig2 encoder can drive LVTMA */
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index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
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num = 2;
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break;
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@ -684,16 +715,15 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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}
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}
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if (radeon_encoder->pixel_clock > 165000) {
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args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
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if (radeon_encoder->pixel_clock > 165000)
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args.ucLaneNum = 8;
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} else {
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if (dig_connector->linkb)
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args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
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else
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args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
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else
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args.ucLaneNum = 4;
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}
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if (dig_connector->linkb)
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args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
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else
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args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
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args.ucEncoderMode = atombios_get_encoder_mode(encoder);
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@ -707,7 +737,7 @@ union dig_transmitter_control {
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};
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static void
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atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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@ -756,6 +786,9 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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args.v1.ucAction = action;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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args.v1.usInitInfo = radeon_connector->connector_object_id;
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} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
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args.v1.asMode.ucLaneSel = lane_num;
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args.v1.asMode.ucLaneSet = lane_set;
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} else {
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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@ -767,6 +800,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
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if (dig->dig_block)
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args.v2.acConfig.ucEncoderSel = 1;
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if (dig_connector->linkb)
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args.v2.acConfig.ucLinkSel = 1;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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@ -792,17 +827,20 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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/* XXX doesn't really matter which dig encoder we pick as long as it's
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* not already in use
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*/
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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if (rdev->flags & RADEON_IS_IGP) {
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if (radeon_encoder->pixel_clock > 165000) {
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args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
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ATOM_TRANSMITTER_CONFIG_LINKA_B);
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if (dig_connector->igp_lane_info & 0x3)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
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else if (dig_connector->igp_lane_info & 0xc)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
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} else {
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
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if (dig_connector->igp_lane_info & 0x1)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else if (dig_connector->igp_lane_info & 0x2)
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@ -812,34 +850,22 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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else if (dig_connector->igp_lane_info & 0x8)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
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}
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} else {
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
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ATOM_TRANSMITTER_CONFIG_LINKA_B |
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ATOM_TRANSMITTER_CONFIG_LANE_0_7);
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else {
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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}
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}
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break;
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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/* Only dig2 encoder can drive LVTMA */
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
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ATOM_TRANSMITTER_CONFIG_LINKA_B |
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ATOM_TRANSMITTER_CONFIG_LANE_0_7);
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else {
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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}
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break;
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}
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if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
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if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
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@ -850,99 +876,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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}
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static void
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atombios_dig_transmitter_setup_vsemph(struct drm_encoder *encoder, u8 lane_num,
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u8 lane_set)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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union dig_transmitter_control args;
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int index = 0, num = 0;
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uint8_t frev, crev;
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struct radeon_encoder_atom_dig *dig;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
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struct radeon_connector_atom_dig *dig_connector;
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connector = radeon_get_connector_for_encoder(encoder);
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if (!connector)
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return;
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radeon_connector = to_radeon_connector(connector);
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if (!radeon_encoder->enc_priv)
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return;
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dig = radeon_encoder->enc_priv;
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if (!radeon_connector->con_priv)
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return;
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dig_connector = radeon_connector->con_priv;
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memset(&args, 0, sizeof(args));
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if (ASIC_IS_DCE32(rdev))
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index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
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else {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
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break;
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}
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}
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atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
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args.v1.ucAction = ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH;
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args.v1.asMode.ucLaneSel = lane_num;
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args.v1.asMode.ucLaneSet = lane_set;
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if (ASIC_IS_DCE32(rdev)) {
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args.v2.acConfig.fDPConnector = 1;
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if (dig->dig_block)
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args.v2.acConfig.ucEncoderSel = 1;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v2.acConfig.ucTransmitterSel = 0;
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num = 0;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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args.v2.acConfig.ucTransmitterSel = 1;
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num = 1;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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args.v2.acConfig.ucTransmitterSel = 2;
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num = 2;
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break;
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}
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} else {
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args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
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if (dig_connector->linkb)
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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else
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args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
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}
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}
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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if (ASIC_IS_DCE32(rdev))
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DRM_INFO("Output UNIPHY%d transmitter VSEMPH setup success\n", num);
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else
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DRM_INFO("Output DIG%d transmitter VSEMPH setup success\n", num);
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}
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static void
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atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
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{
|
||||
|
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@ -1150,13 +1083,33 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
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args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
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else
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args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
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} else
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args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
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} else {
|
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
|
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struct radeon_connector_atom_dig *dig_connector;
|
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|
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connector = radeon_get_connector_for_encoder(encoder);
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if (!connector)
|
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return;
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radeon_connector = to_radeon_connector(connector);
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if (!radeon_connector->con_priv)
|
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return;
|
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dig_connector = radeon_connector->con_priv;
|
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|
||||
/* XXX doesn't really matter which dig encoder we pick as long as it's
|
||||
* not already in use
|
||||
*/
|
||||
if (dig_connector->linkb)
|
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args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
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else
|
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args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
|
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}
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break;
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
|
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args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
|
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break;
|
||||
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
|
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/* Only dig2 encoder can drive LVTMA */
|
||||
args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
|
||||
break;
|
||||
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
|
||||
|
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@ -1259,14 +1212,14 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
|
|||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
|
||||
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
|
||||
/* disable the encoder and transmitter */
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
|
||||
atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
|
||||
|
||||
/* setup and enable the encoder and transmitter */
|
||||
atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
|
||||
break;
|
||||
case ENCODER_OBJECT_ID_INTERNAL_DDI:
|
||||
atombios_ddia_setup(encoder, ATOM_ENABLE);
|
||||
|
|
|
|||
|
|
@ -335,7 +335,7 @@ struct radeon_connector_atom_dig {
|
|||
bool linkb;
|
||||
uint16_t uc_i2c_id;
|
||||
struct radeon_i2c_chan *dp_i2c_bus;
|
||||
u8 dpcp[8];
|
||||
u8 dpcd[8];
|
||||
};
|
||||
|
||||
struct radeon_connector {
|
||||
|
|
@ -362,7 +362,7 @@ struct radeon_framebuffer {
|
|||
};
|
||||
|
||||
extern int radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
|
||||
extern void radeon_dp_getdpcp(struct radeon_connector *connector);
|
||||
extern void radeon_dp_getdpcd(struct radeon_connector *connector);
|
||||
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
|
||||
uint8_t write_byte, uint8_t *read_byte);
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
#define AUX_I2C_REPLY_MASK (0x3 << 6)
|
||||
|
||||
/* AUX CH addresses */
|
||||
#define DP_DPCP_REV 0x0
|
||||
#define DP_DPCD_REV 0x0
|
||||
|
||||
#define DP_LINK_BW_SET 0x100
|
||||
# define DP_LINK_BW_1_62 0x06
|
||||
|
|
@ -132,6 +132,8 @@
|
|||
#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
|
||||
#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
|
||||
|
||||
#define DP_SET_POWER 0x600
|
||||
|
||||
#define MODE_I2C_START 1
|
||||
#define MODE_I2C_WRITE 2
|
||||
#define MODE_I2C_READ 4
|
||||
|
|
|
|||
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Ссылка в новой задаче