pch_phub: add new device ML7213
Add ML7213 device information. ML7213 is companion chip of Intel Atom E6xx series for IVI(In-Vehicle Infotainment). ML7213 is completely compatible for Intel EG20T PCH. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Tomoya MORINAGA
Greg Kroah-Hartman
Родитель
ed43b47b29
Коммит
1a738dcf6d
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@ -441,7 +441,7 @@ config BMP085
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module will be called bmp085.
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config PCH_PHUB
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tristate "PCH Packet Hub of Intel Topcliff"
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tristate "PCH Packet Hub of Intel Topcliff / OKI SEMICONDUCTOR ML7213"
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depends on PCI
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help
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This driver is for PCH(Platform controller Hub) PHUB(Packet Hub) of
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@ -449,6 +449,11 @@ config PCH_PHUB
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processor. The Topcliff has MAC address and Option ROM data in SROM.
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This driver can access MAC address and Option ROM data in SROM.
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This driver also can be used for OKI SEMICONDUCTOR's ML7213 which is
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for IVI(In-Vehicle Infotainment) use.
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ML7213 is companion chip for Intel Atom E6xx series.
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ML7213 is completely compatible for Intel EG20T PCH.
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To compile this driver as a module, choose M here: the module will
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be called pch_phub.
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
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* Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -33,7 +33,12 @@
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#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
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#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
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#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
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#define PCH_PHUB_ROM_START_ADDR 0x14 /* ROM data area start address offset */
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#define PCH_PHUB_MAC_START_ADDR 0x20C /* MAC data area start address offset */
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#define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset
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(Intel EG20T PCH)*/
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#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
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offset(OKI SEMICONDUCTOR ML7213)
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*/
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/* MAX number of INT_REDUCE_CONTROL registers */
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#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
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@ -42,6 +47,10 @@
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#define CLKCFG_CAN_50MHZ 0x12000000
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#define CLKCFG_CANCLK_MASK 0xFF000000
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/* Macros for ML7213 */
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
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/* SROM ACCESS Macro */
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#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
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@ -298,7 +307,7 @@ static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
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{
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unsigned int mem_addr;
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mem_addr = PCH_PHUB_ROM_START_ADDR +
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mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
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pch_phub_mac_offset[offset_address];
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pch_phub_read_serial_rom(chip, mem_addr, data);
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@ -315,7 +324,7 @@ static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
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int retval;
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unsigned int mem_addr;
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mem_addr = PCH_PHUB_ROM_START_ADDR +
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mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
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pch_phub_mac_offset[offset_address];
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retval = pch_phub_write_serial_rom(chip, mem_addr, data);
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@ -594,9 +603,9 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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"pch_phub_extrom_base_address variable is %p\n", __func__,
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chip->pch_phub_extrom_base_address);
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pci_set_drvdata(pdev, chip);
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retval = sysfs_create_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
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if (id->driver_data == 1) {
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retval = sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_pch_mac.attr);
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if (retval)
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goto err_sysfs_create;
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@ -604,13 +613,28 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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if (retval)
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goto exit_bin_attr;
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pch_phub_read_modify_write_reg(chip, (unsigned int)CLKCFG_REG_OFFSET,
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CLKCFG_CAN_50MHZ, CLKCFG_CANCLK_MASK);
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pch_phub_read_modify_write_reg(chip,
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(unsigned int)CLKCFG_REG_OFFSET,
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CLKCFG_CAN_50MHZ,
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CLKCFG_CANCLK_MASK);
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/* set the prefech value */
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iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
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/* set the interrupt delay value */
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iowrite32(0x25, chip->pch_phub_base_address + 0x44);
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} else if (id->driver_data == 2) {
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retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
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if (retval)
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goto err_sysfs_create;
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/* set the prefech value
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* Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
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* Device4(SDIO #0,1,2):f
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* Device6(SATA 2):f
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* Device8(USB OHCI #0/ USB EHCI #0):a
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*/
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iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
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}
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pci_set_drvdata(pdev, chip);
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return 0;
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exit_bin_attr:
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@ -687,8 +711,9 @@ static int pch_phub_resume(struct pci_dev *pdev)
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#endif /* CONFIG_PM */
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static struct pci_device_id pch_phub_pcidev_id[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH1_PHUB)},
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{0,}
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
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{ }
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};
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static struct pci_driver pch_phub_driver = {
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