mvebu drivers (mbus and pci) fixes for v3.15
- pci - fix off-by-one for mbus window size - split BARs into multiple mbus windows when needed - mbus - avoid setting undefined window size - allow several windows with the same target/attr -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTX6KOAAoJEP45WPkGe8ZnK14QAJoddpkgzp7sgANXpE3SlpA/ FycxazhA8s4giZKiPcFy93sl8SYEvpB8l9UDRhvImTlbifrB+PpBBQf77RyAH3w9 vJIwuLC2BwLJEaY4CzA0ahIvhhik/nextB4btVQoh0iqxix9Elk+BZh7QspCxYkC vkGdFoEiLuI73SxMv2qNMhfz24UbrctZwZlMxRB1Lbo0YCY8SkQMeK8d4ZwzNHhx 10jyGcpINQcUb5Z5vmyGrdvOEFTmOWcn5gflNpj1keKfHbdzDRomrPzX99udWMll 0tAuCcK8iW7kG2w5RiBU9IPd7eVgi3lf6tZmUB4JEYak8W7C/TcjxfRSdMNU7G/k dwDHcmD67UOvLlOwoZW5eCG1tmyUfAeTwKxZKAR97tkiXdcEK49EsY348LEWzQuo ZG2OLvjXwBo8y5kOHIOd3cZAdmTh9HSt1HgZkzU+vZFZWQAcM8PRKaR7/dyovTq8 gUUifjjQ1HHzlOAJ12j3C98jUDts64sJCB54CXDTJlWZn3fw3cYiZJhrJJtpdGn5 94GGwUvLX1dd9uSV1rq6/1tJc7q7IpgdWSjiPUE2zyXL91PLmElB7wjrsyphBAcJ 0QWx1j8V6fBDtveYfjwzMDhYDjZGqkJHV1L5k+NEy2VsgrT3aX9EkbHnYRsS6jNb 9fmP83qeahAZusCEqQ2v =b3o7 -----END PGP SIGNATURE----- Merge tag 'mvebu-mbus_pci-fixes-3.15' of git://git.infradead.org/linux-mvebu into fixes From Jason Cooper: mvebu drivers (mbus and pci) fixes for v3.15 - pci - fix off-by-one for mbus window size - split BARs into multiple mbus windows when needed - mbus - avoid setting undefined window size - allow several windows with the same target/attr * tag 'mvebu-mbus_pci-fixes-3.15' of git://git.infradead.org/linux-mvebu: PCI: mvebu: split PCIe BARs into multiple MBus windows when needed bus: mvebu-mbus: allow several windows with the same target/attribute bus: mvebu-mbus: Avoid setting an undefined window size PCI: mvebu: fix off-by-one in the computed size of the mbus windows Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Коммит
1a7adf2e23
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@ -56,6 +56,7 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/debugfs.h>
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#include <linux/log2.h>
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/*
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* DDR target is the same on all platforms.
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@ -222,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
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*/
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if ((u64)base < wend && end > wbase)
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return 0;
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/*
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* Check if target/attribute conflicts
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*/
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if (target == wtarget && attr == wattr)
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return 0;
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}
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return 1;
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@ -266,6 +261,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
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mbus->soc->win_cfg_offset(win);
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u32 ctrl, remap_addr;
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if (!is_power_of_2(size)) {
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WARN(true, "Invalid MBus window size: 0x%zx\n", size);
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return -EINVAL;
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}
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if ((base & (phys_addr_t)(size - 1)) != 0) {
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WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
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size);
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return -EINVAL;
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}
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ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
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(attr << WIN_CTRL_ATTR_SHIFT) |
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(target << WIN_CTRL_TGT_SHIFT) |
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@ -413,6 +419,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
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win, (unsigned long long)wbase,
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(unsigned long long)(wbase + wsize), wtarget, wattr);
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if (!is_power_of_2(wsize) ||
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((wbase & (u64)(wsize - 1)) != 0))
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seq_puts(seq, " (Invalid base/size!!)");
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if (win < mbus->soc->num_remappable_wins) {
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seq_printf(seq, " (remap %016llx)\n",
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(unsigned long long)wremap);
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@ -293,6 +293,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* Remove windows, starting from the largest ones to the smallest
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* ones.
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*/
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static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
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phys_addr_t base, size_t size)
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{
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while (size) {
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size_t sz = 1 << (fls(size) - 1);
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mvebu_mbus_del_window(base, sz);
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base += sz;
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size -= sz;
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}
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}
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/*
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* MBus windows can only have a power of two size, but PCI BARs do not
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* have this constraint. Therefore, we have to split the PCI BAR into
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* areas each having a power of two size. We start from the largest
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* one (i.e highest order bit set in the size).
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*/
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static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
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unsigned int target, unsigned int attribute,
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phys_addr_t base, size_t size,
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phys_addr_t remap)
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{
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size_t size_mapped = 0;
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while (size) {
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size_t sz = 1 << (fls(size) - 1);
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int ret;
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ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
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sz, remap);
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if (ret) {
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dev_err(&port->pcie->pdev->dev,
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"Could not create MBus window at 0x%x, size 0x%x: %d\n",
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base, sz, ret);
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mvebu_pcie_del_windows(port, base - size_mapped,
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size_mapped);
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return;
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}
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size -= sz;
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size_mapped += sz;
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base += sz;
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if (remap != MVEBU_MBUS_NO_REMAP)
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remap += sz;
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}
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}
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static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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{
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phys_addr_t iobase;
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@ -304,8 +356,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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/* If a window was configured, remove it */
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if (port->iowin_base) {
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mvebu_mbus_del_window(port->iowin_base,
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port->iowin_size);
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mvebu_pcie_del_windows(port, port->iowin_base,
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port->iowin_size);
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port->iowin_base = 0;
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port->iowin_size = 0;
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}
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@ -331,11 +383,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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port->iowin_base = port->pcie->io.start + iobase;
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port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
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(port->bridge.iolimitupper << 16)) -
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iobase);
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iobase) + 1;
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mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
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port->iowin_base, port->iowin_size,
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iobase);
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mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
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port->iowin_base, port->iowin_size,
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iobase);
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}
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static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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@ -346,8 +398,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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/* If a window was configured, remove it */
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if (port->memwin_base) {
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mvebu_mbus_del_window(port->memwin_base,
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port->memwin_size);
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mvebu_pcie_del_windows(port, port->memwin_base,
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port->memwin_size);
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port->memwin_base = 0;
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port->memwin_size = 0;
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}
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@ -364,10 +416,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
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port->memwin_size =
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(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
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port->memwin_base;
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port->memwin_base + 1;
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mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
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port->memwin_base, port->memwin_size);
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mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
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port->memwin_base, port->memwin_size,
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MVEBU_MBUS_NO_REMAP);
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}
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/*
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@ -743,14 +796,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
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/*
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* On the PCI-to-PCI bridge side, the I/O windows must have at
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* least a 64 KB size and be aligned on their size, and the
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* memory windows must have at least a 1 MB size and be
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* aligned on their size
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* least a 64 KB size and the memory windows must have at
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* least a 1 MB size. Moreover, MBus windows need to have a
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* base address aligned on their size, and their size must be
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* a power of two. This means that if the BAR doesn't have a
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* power of two size, several MBus windows will actually be
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* created. We need to ensure that the biggest MBus window
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* (which will be the first one) is aligned on its size, which
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* explains the rounddown_pow_of_two() being done here.
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*/
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if (res->flags & IORESOURCE_IO)
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return round_up(start, max_t(resource_size_t, SZ_64K, size));
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return round_up(start, max_t(resource_size_t, SZ_64K,
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rounddown_pow_of_two(size)));
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else if (res->flags & IORESOURCE_MEM)
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return round_up(start, max_t(resource_size_t, SZ_1M, size));
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return round_up(start, max_t(resource_size_t, SZ_1M,
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rounddown_pow_of_two(size)));
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else
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return start;
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}
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