irqchip: GICv3: ITS: tables allocators
The interrupt translation is driven by a set of tables (device, ITT, and collection) to be in the end delivered to a CPU. Also, the redistributors rely on a couple of tables (configuration, and pending) to deliver the interrupts to the CPUs. This patch adds the required allocators for these tables. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-8-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Marc Zyngier
Jason Cooper
Родитель
bf9529f8c8
Коммит
1ac19ca6bf
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@ -91,6 +91,14 @@ struct its_device {
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u32 device_id;
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u32 device_id;
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};
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};
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static LIST_HEAD(its_nodes);
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static DEFINE_SPINLOCK(its_lock);
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static struct device_node *gic_root_node;
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static struct rdists *gic_rdists;
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#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
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#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
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/*
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/*
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* ITS command descriptors - parameters to be encoded in a command
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* ITS command descriptors - parameters to be encoded in a command
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* block.
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* block.
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@ -689,3 +697,287 @@ static void its_lpi_free(unsigned long *bitmap, int base, int nr_ids)
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kfree(bitmap);
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kfree(bitmap);
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}
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}
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/*
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* We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
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* deal with (one configuration byte per interrupt). PENDBASE has to
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* be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
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*/
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#define LPI_PROPBASE_SZ SZ_64K
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#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
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/*
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* This is how many bits of ID we need, including the useless ones.
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*/
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#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
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#define LPI_PROP_DEFAULT_PRIO 0xa0
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static int __init its_alloc_lpi_tables(void)
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{
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phys_addr_t paddr;
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gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
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get_order(LPI_PROPBASE_SZ));
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if (!gic_rdists->prop_page) {
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pr_err("Failed to allocate PROPBASE\n");
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return -ENOMEM;
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}
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paddr = page_to_phys(gic_rdists->prop_page);
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pr_info("GIC: using LPI property table @%pa\n", &paddr);
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/* Priority 0xa0, Group-1, disabled */
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memset(page_address(gic_rdists->prop_page),
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LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
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LPI_PROPBASE_SZ);
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/* Make sure the GIC will observe the written configuration */
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__flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
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return 0;
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}
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static const char *its_base_type_string[] = {
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[GITS_BASER_TYPE_DEVICE] = "Devices",
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[GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
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[GITS_BASER_TYPE_CPU] = "Physical CPUs",
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[GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
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[GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
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[GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
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[GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
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};
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static void its_free_tables(struct its_node *its)
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{
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int i;
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for (i = 0; i < GITS_BASER_NR_REGS; i++) {
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if (its->tables[i]) {
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free_page((unsigned long)its->tables[i]);
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its->tables[i] = NULL;
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}
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}
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}
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static int its_alloc_tables(struct its_node *its)
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{
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int err;
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int i;
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int psz = PAGE_SIZE;
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u64 shr = GITS_BASER_InnerShareable;
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for (i = 0; i < GITS_BASER_NR_REGS; i++) {
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u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
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u64 type = GITS_BASER_TYPE(val);
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u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
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u64 tmp;
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void *base;
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if (type == GITS_BASER_TYPE_NONE)
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continue;
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/* We're lazy and only allocate a single page for now */
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base = (void *)get_zeroed_page(GFP_KERNEL);
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if (!base) {
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err = -ENOMEM;
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goto out_free;
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}
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its->tables[i] = base;
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retry_baser:
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val = (virt_to_phys(base) |
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(type << GITS_BASER_TYPE_SHIFT) |
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((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
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GITS_BASER_WaWb |
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shr |
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GITS_BASER_VALID);
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switch (psz) {
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case SZ_4K:
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val |= GITS_BASER_PAGE_SIZE_4K;
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break;
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case SZ_16K:
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val |= GITS_BASER_PAGE_SIZE_16K;
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break;
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case SZ_64K:
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val |= GITS_BASER_PAGE_SIZE_64K;
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break;
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}
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val |= (PAGE_SIZE / psz) - 1;
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writeq_relaxed(val, its->base + GITS_BASER + i * 8);
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tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
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if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
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/*
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* Shareability didn't stick. Just use
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* whatever the read reported, which is likely
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* to be the only thing this redistributor
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* supports.
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*/
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shr = tmp & GITS_BASER_SHAREABILITY_MASK;
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goto retry_baser;
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}
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if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
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/*
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* Page size didn't stick. Let's try a smaller
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* size and retry. If we reach 4K, then
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* something is horribly wrong...
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*/
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switch (psz) {
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case SZ_16K:
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psz = SZ_4K;
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goto retry_baser;
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case SZ_64K:
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psz = SZ_16K;
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goto retry_baser;
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}
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}
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if (val != tmp) {
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pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
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its->msi_chip.of_node->full_name, i,
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(unsigned long) val, (unsigned long) tmp);
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err = -ENXIO;
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goto out_free;
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}
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pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
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(int)(PAGE_SIZE / entry_size),
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its_base_type_string[type],
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(unsigned long)virt_to_phys(base),
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psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
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}
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return 0;
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out_free:
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its_free_tables(its);
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return err;
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}
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static int its_alloc_collections(struct its_node *its)
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{
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its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
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GFP_KERNEL);
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if (!its->collections)
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return -ENOMEM;
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return 0;
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}
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static void its_cpu_init_lpis(void)
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{
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void __iomem *rbase = gic_data_rdist_rd_base();
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struct page *pend_page;
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u64 val, tmp;
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/* If we didn't allocate the pending table yet, do it now */
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pend_page = gic_data_rdist()->pend_page;
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if (!pend_page) {
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phys_addr_t paddr;
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/*
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* The pending pages have to be at least 64kB aligned,
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* hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
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*/
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pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
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get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
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if (!pend_page) {
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pr_err("Failed to allocate PENDBASE for CPU%d\n",
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smp_processor_id());
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return;
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}
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/* Make sure the GIC will observe the zero-ed page */
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__flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
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paddr = page_to_phys(pend_page);
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pr_info("CPU%d: using LPI pending table @%pa\n",
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smp_processor_id(), &paddr);
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gic_data_rdist()->pend_page = pend_page;
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}
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/* Disable LPIs */
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val = readl_relaxed(rbase + GICR_CTLR);
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val &= ~GICR_CTLR_ENABLE_LPIS;
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writel_relaxed(val, rbase + GICR_CTLR);
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/*
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* Make sure any change to the table is observable by the GIC.
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*/
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dsb(sy);
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/* set PROPBASE */
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val = (page_to_phys(gic_rdists->prop_page) |
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GICR_PROPBASER_InnerShareable |
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GICR_PROPBASER_WaWb |
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((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
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writeq_relaxed(val, rbase + GICR_PROPBASER);
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tmp = readq_relaxed(rbase + GICR_PROPBASER);
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if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
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pr_info_once("GIC: using cache flushing for LPI property table\n");
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gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
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}
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/* set PENDBASE */
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val = (page_to_phys(pend_page) |
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GICR_PROPBASER_InnerShareable |
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GICR_PROPBASER_WaWb);
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writeq_relaxed(val, rbase + GICR_PENDBASER);
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/* Enable LPIs */
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val = readl_relaxed(rbase + GICR_CTLR);
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val |= GICR_CTLR_ENABLE_LPIS;
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writel_relaxed(val, rbase + GICR_CTLR);
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/* Make sure the GIC has seen the above */
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dsb(sy);
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}
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static void its_cpu_init_collection(void)
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{
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struct its_node *its;
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int cpu;
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spin_lock(&its_lock);
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cpu = smp_processor_id();
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list_for_each_entry(its, &its_nodes, entry) {
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u64 target;
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/*
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* We now have to bind each collection to its target
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* redistributor.
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*/
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if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
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/*
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* This ITS wants the physical address of the
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* redistributor.
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*/
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target = gic_data_rdist()->phys_base;
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} else {
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/*
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* This ITS wants a linear CPU number.
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*/
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target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
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target = GICR_TYPER_CPU_NUMBER(target);
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}
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/* Perform collection mapping */
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its->collections[cpu].target_address = target;
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its->collections[cpu].col_id = cpu;
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its_send_mapc(its, &its->collections[cpu], 1);
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its_send_invall(its, &its->collections[cpu]);
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}
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spin_unlock(&its_lock);
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}
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