iio: adc: Add support for STM32 ADC core
Add core driver for STMicroelectronics STM32 ADC (Analog to Digital Converter). STM32 ADC can be composed of up to 3 ADCs with shared resources like clock prescaler, common interrupt line and analog reference voltage. This core driver basically manages shared resources. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
Родитель
841fcea454
Коммит
1add698802
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@ -441,6 +441,18 @@ config ROCKCHIP_SARADC
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To compile this driver as a module, choose M here: the
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module will be called rockchip_saradc.
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config STM32_ADC_CORE
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tristate "STMicroelectronics STM32 adc core"
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depends on ARCH_STM32 || COMPILE_TEST
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depends on OF
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depends on REGULATOR
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help
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Select this option to enable the core driver for STMicroelectronics
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STM32 analog-to-digital converter (ADC).
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This driver can also be built as a module. If so, the module
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will be called stm32-adc-core.
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config STX104
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tristate "Apex Embedded Systems STX104 driver"
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depends on X86 && ISA_BUS_API
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@ -43,6 +43,7 @@ obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
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obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_STX104) += stx104.o
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obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
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obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
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obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
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obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
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@ -0,0 +1,303 @@
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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* Inspired from: fsl-imx25-tsadc
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*
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* License type: GPLv2
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "stm32-adc-core.h"
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/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
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#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
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/* STM32F4_ADC_CSR - bit fields */
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#define STM32F4_EOC3 BIT(17)
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#define STM32F4_EOC2 BIT(9)
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#define STM32F4_EOC1 BIT(1)
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/* STM32F4_ADC_CCR - bit fields */
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#define STM32F4_ADC_ADCPRE_SHIFT 16
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#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
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/* STM32 F4 maximum analog clock rate (from datasheet) */
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#define STM32F4_ADC_MAX_CLK_RATE 36000000
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/**
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* struct stm32_adc_priv - stm32 ADC core private data
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* @irq: irq for ADC block
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* @domain: irq domain reference
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* @aclk: clock reference for the analog circuitry
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* @vref: regulator reference
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* @common: common data for all ADC instances
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*/
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struct stm32_adc_priv {
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int irq;
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struct irq_domain *domain;
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struct clk *aclk;
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struct regulator *vref;
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struct stm32_adc_common common;
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};
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static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
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{
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return container_of(com, struct stm32_adc_priv, common);
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}
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/* STM32F4 ADC internal common clock prescaler division ratios */
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static int stm32f4_pclk_div[] = {2, 4, 6, 8};
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/**
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* stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
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* @priv: stm32 ADC core private data
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* Select clock prescaler used for analog conversions, before using ADC.
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*/
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static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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unsigned long rate;
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u32 val;
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int i;
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rate = clk_get_rate(priv->aclk);
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for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
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if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
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break;
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}
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if (i >= ARRAY_SIZE(stm32f4_pclk_div))
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return -EINVAL;
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val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
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val &= ~STM32F4_ADC_ADCPRE_MASK;
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val |= i << STM32F4_ADC_ADCPRE_SHIFT;
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writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
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dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
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rate / (stm32f4_pclk_div[i] * 1000));
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return 0;
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}
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/* ADC common interrupt for all instances */
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static void stm32_adc_irq_handler(struct irq_desc *desc)
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{
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struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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chained_irq_enter(chip, desc);
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status = readl_relaxed(priv->common.base + STM32F4_ADC_CSR);
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if (status & STM32F4_EOC1)
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generic_handle_irq(irq_find_mapping(priv->domain, 0));
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if (status & STM32F4_EOC2)
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generic_handle_irq(irq_find_mapping(priv->domain, 1));
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if (status & STM32F4_EOC3)
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generic_handle_irq(irq_find_mapping(priv->domain, 2));
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chained_irq_exit(chip, desc);
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};
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static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, d->host_data);
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
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return 0;
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}
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static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops stm32_adc_domain_ops = {
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.map = stm32_adc_domain_map,
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.unmap = stm32_adc_domain_unmap,
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.xlate = irq_domain_xlate_onecell,
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};
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static int stm32_adc_irq_probe(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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struct device_node *np = pdev->dev.of_node;
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priv->irq = platform_get_irq(pdev, 0);
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if (priv->irq < 0) {
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dev_err(&pdev->dev, "failed to get irq\n");
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return priv->irq;
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}
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priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
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&stm32_adc_domain_ops,
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priv);
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if (!priv->domain) {
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dev_err(&pdev->dev, "Failed to add irq domain\n");
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return -ENOMEM;
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}
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irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
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irq_set_handler_data(priv->irq, priv);
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return 0;
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}
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static void stm32_adc_irq_remove(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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int hwirq;
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for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
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irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
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irq_domain_remove(priv->domain);
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irq_set_chained_handler(priv->irq, NULL);
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}
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static int stm32_adc_probe(struct platform_device *pdev)
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{
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struct stm32_adc_priv *priv;
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->common.base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->common.base))
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return PTR_ERR(priv->common.base);
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priv->vref = devm_regulator_get(&pdev->dev, "vref");
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if (IS_ERR(priv->vref)) {
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ret = PTR_ERR(priv->vref);
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dev_err(&pdev->dev, "vref get failed, %d\n", ret);
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return ret;
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}
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ret = regulator_enable(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref enable failed\n");
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return ret;
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}
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ret = regulator_get_voltage(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
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goto err_regulator_disable;
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}
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priv->common.vref_mv = ret / 1000;
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dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
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priv->aclk = devm_clk_get(&pdev->dev, "adc");
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if (IS_ERR(priv->aclk)) {
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ret = PTR_ERR(priv->aclk);
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dev_err(&pdev->dev, "Can't get 'adc' clock\n");
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goto err_regulator_disable;
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}
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ret = clk_prepare_enable(priv->aclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_regulator_disable;
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}
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ret = stm32f4_adc_clk_sel(pdev, priv);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk selection failed\n");
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goto err_clk_disable;
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}
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ret = stm32_adc_irq_probe(pdev, priv);
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if (ret < 0)
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goto err_clk_disable;
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platform_set_drvdata(pdev, &priv->common);
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ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to populate DT children\n");
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goto err_irq_remove;
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}
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return 0;
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err_irq_remove:
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stm32_adc_irq_remove(pdev, priv);
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err_clk_disable:
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clk_disable_unprepare(priv->aclk);
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err_regulator_disable:
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regulator_disable(priv->vref);
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return ret;
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}
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static int stm32_adc_remove(struct platform_device *pdev)
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{
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struct stm32_adc_common *common = platform_get_drvdata(pdev);
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struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
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of_platform_depopulate(&pdev->dev);
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stm32_adc_irq_remove(pdev, priv);
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clk_disable_unprepare(priv->aclk);
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regulator_disable(priv->vref);
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return 0;
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}
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static const struct of_device_id stm32_adc_of_match[] = {
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{ .compatible = "st,stm32f4-adc-core" },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
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static struct platform_driver stm32_adc_driver = {
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.probe = stm32_adc_probe,
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.remove = stm32_adc_remove,
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.driver = {
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.name = "stm32-adc-core",
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.of_match_table = stm32_adc_of_match,
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},
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};
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module_platform_driver(stm32_adc_driver);
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MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:stm32-adc-core");
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@ -0,0 +1,52 @@
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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* License type: GPLv2
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __STM32_ADC_H
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#define __STM32_ADC_H
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/*
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* STM32 - ADC global register map
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* ________________________________________________________
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* | Offset | Register |
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* --------------------------------------------------------
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* | 0x000 | Master ADC1 |
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* --------------------------------------------------------
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* | 0x100 | Slave ADC2 |
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* --------------------------------------------------------
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* | 0x200 | Slave ADC3 |
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* --------------------------------------------------------
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* | 0x300 | Master & Slave common regs |
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* --------------------------------------------------------
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*/
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#define STM32_ADC_MAX_ADCS 3
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#define STM32_ADCX_COMN_OFFSET 0x300
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/**
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* struct stm32_adc_common - stm32 ADC driver common data (for all instances)
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* @base: control registers base cpu addr
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* @vref_mv: vref voltage (mv)
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*/
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struct stm32_adc_common {
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void __iomem *base;
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int vref_mv;
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};
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#endif
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