Merge branch 'upstream' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev
This commit is contained in:
Linus Torvalds
Коммит
1b11d78cf8
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@ -68,8 +68,8 @@ enum {
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PIIX_COMB_PATA_P0 = (1 << 1),
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PIIX_COMB = (1 << 2), /* combined mode enabled? */
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PIIX_PORT_PRESENT = (1 << 0),
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PIIX_PORT_ENABLED = (1 << 4),
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PIIX_PORT_ENABLED = (1 << 0),
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PIIX_PORT_PRESENT = (1 << 4),
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PIIX_80C_PRI = (1 << 5) | (1 << 4),
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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@ -377,7 +377,9 @@ static void piix_pata_phy_reset(struct ata_port *ap)
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* None (inherited from caller).
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*
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* RETURNS:
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* Non-zero if device detected, zero otherwise.
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* Non-zero if port is enabled, it may or may not have a device
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* attached in that case (PRESENT bit would only be set if BIOS probe
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* was done). Zero is returned if port is disabled.
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*/
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static int piix_sata_probe (struct ata_port *ap)
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{
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@ -401,7 +403,7 @@ static int piix_sata_probe (struct ata_port *ap)
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*/
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for (i = 0; i < 4; i++) {
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mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
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mask = (PIIX_PORT_ENABLED << i);
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if ((orig_mask & mask) == mask)
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if (combined || (i == ap->hard_port_no))
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@ -52,7 +52,10 @@ enum {
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/* PCI configuration registers */
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SIS_GENCTL = 0x54, /* IDE General Control register */
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SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
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SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
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SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
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SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
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SIS_PMR = 0x90, /* port mapping register */
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SIS_PMR_COMBINED = 0x30,
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/* random bits */
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SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
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@ -67,6 +70,7 @@ static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static struct pci_device_id sis_pci_tbl[] = {
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{ PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
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{ PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
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{ PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
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{ } /* terminate list */
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};
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@ -139,56 +143,94 @@ MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
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static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
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{
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unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
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if (port_no)
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addr += SIS_SATA1_OFS;
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if (port_no)
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if (device == 0x182)
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addr += SIS182_SATA1_OFS;
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else
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addr += SIS180_SATA1_OFS;
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return addr;
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}
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static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
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u32 val;
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
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u32 val, val2;
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u8 pmr;
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if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return 0xffffffff;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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pci_read_config_dword(pdev, cfg_addr, &val);
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return val;
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
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return val|val2;
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}
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static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
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unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
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u8 pmr;
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if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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pci_write_config_dword(pdev, cfg_addr, val);
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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pci_write_config_dword(pdev, cfg_addr+0x10, val);
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}
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static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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u32 val,val2;
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u8 pmr;
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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if (ap->flags & SIS_FLAG_CFGSCR)
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return sis_scr_cfg_read(ap, sc_reg);
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return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
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return val|val2;
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}
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
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u8 pmr;
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if (sc_reg > SCR_CONTROL)
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return;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if (ap->flags & SIS_FLAG_CFGSCR)
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sis_scr_cfg_write(ap, sc_reg, val);
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else
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else {
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outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
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outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
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}
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}
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/* move to PCI layer, integrate w/ MSI stuff */
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@ -210,6 +252,8 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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u32 genctl;
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struct ata_port_info *ppi;
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int pci_dev_busy = 0;
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u8 pmr;
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u8 port2_start;
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rc = pci_enable_device(pdev);
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if (rc)
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@ -251,11 +295,27 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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probe_ent->host_flags |= SIS_FLAG_CFGSCR;
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}
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if (ent->device != 0x182) {
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if ((pmr & SIS_PMR_COMBINED) == 0) {
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printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in SATA mode\n");
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port2_start=0x64;
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}
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else {
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printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in combined mode\n");
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port2_start=0;
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}
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}
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else {
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printk(KERN_INFO "sata_sis: Detected SiS 182 chipset\n");
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port2_start = 0x20;
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}
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if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
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probe_ent->port[0].scr_addr =
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pci_resource_start(pdev, SIS_SCR_PCI_BAR);
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probe_ent->port[1].scr_addr =
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pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
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pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
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}
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pci_set_master(pdev);
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