[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
f0c8ac8083
Коммит
1b3c5cdab4
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@ -182,27 +182,6 @@
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interrupt-parent = <&mpc5200_pic>;
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};
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pci@0d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "mpc5200-pci";
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reg = <d00 100>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
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c000 0 0 2 &mpc5200_pic 0 0 3
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c000 0 0 3 &mpc5200_pic 0 0 3
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c000 0 0 4 &mpc5200_pic 0 0 3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 b0000000 0 01000000>;
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};
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spi@f00 {
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device_type = "spi";
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compatible = "mpc5200-spi";
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@ -337,4 +316,25 @@
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reg = <8000 4000>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "mpc5200-pci";
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reg = <f0000d00 100>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
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c000 0 0 2 &mpc5200_pic 0 0 3
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c000 0 0 3 &mpc5200_pic 0 0 3
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c000 0 0 4 &mpc5200_pic 0 0 3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 b0000000 0 01000000>;
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};
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};
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@ -182,32 +182,6 @@
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interrupt-parent = <&mpc5200_pic>;
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};
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pci@0d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "mpc5200b-pci\0mpc5200-pci";
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reg = <d00 100>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
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c000 0 0 2 &mpc5200_pic 1 1 3
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c000 0 0 3 &mpc5200_pic 1 2 3
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c000 0 0 4 &mpc5200_pic 1 3 3
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c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
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c800 0 0 2 &mpc5200_pic 1 2 3
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c800 0 0 3 &mpc5200_pic 1 3 3
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c800 0 0 4 &mpc5200_pic 0 0 3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 b0000000 0 01000000>;
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};
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spi@f00 {
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device_type = "spi";
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compatible = "mpc5200b-spi\0mpc5200-spi";
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@ -342,4 +316,30 @@
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reg = <8000 4000>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "mpc5200b-pci\0mpc5200-pci";
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reg = <f0000d00 100>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
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c000 0 0 2 &mpc5200_pic 1 1 3
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c000 0 0 3 &mpc5200_pic 1 2 3
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c000 0 0 4 &mpc5200_pic 1 3 3
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c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
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c800 0 0 2 &mpc5200_pic 1 2 3
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c800 0 0 3 &mpc5200_pic 1 3 3
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c800 0 0 4 &mpc5200_pic 0 0 3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 b0000000 0 01000000>;
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};
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};
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@ -150,36 +150,6 @@
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interrupt-parent = < &ipic >;
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};
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pci@8500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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7000 0 0 1 &ipic 12 8
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7000 0 0 2 &ipic 12 8
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7000 0 0 3 &ipic 12 8
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7000 0 0 4 &ipic 12 8
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/* IDSEL 0x0F - PCI slot */
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7800 0 0 1 &ipic 11 8
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7800 0 0 2 &ipic 12 8
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7800 0 0 3 &ipic 11 8
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7800 0 0 4 &ipic 12 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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@ -208,4 +178,34 @@
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device_type = "ipic";
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};
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};
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pci@e0008500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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7000 0 0 1 &ipic 12 8
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7000 0 0 2 &ipic 12 8
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7000 0 0 3 &ipic 12 8
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7000 0 0 4 &ipic 12 8
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/* IDSEL 0x0F - PCI slot */
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7800 0 0 1 &ipic 11 8
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7800 0 0 2 &ipic 12 8
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7800 0 0 3 &ipic 11 8
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7800 0 0 4 &ipic 12 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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@ -97,65 +97,6 @@
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descriptor-types-mask = <0122003f>;
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};
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pci@8500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 AD17 */
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8800 0 0 1 &ipic 14 8
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8800 0 0 2 &ipic 15 8
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8800 0 0 3 &ipic 16 8
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8800 0 0 4 &ipic 17 8
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/* IDSEL 0x12 AD18 */
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9000 0 0 1 &ipic 16 8
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9000 0 0 2 &ipic 17 8
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9000 0 0 3 &ipic 14 8
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9000 0 0 4 &ipic 15 8
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/* IDSEL 0x13 AD19 */
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9800 0 0 1 &ipic 17 8
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9800 0 0 2 &ipic 14 8
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9800 0 0 3 &ipic 15 8
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9800 0 0 4 &ipic 16 8
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/* IDSEL 0x15 AD21*/
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a800 0 0 1 &ipic 14 8
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a800 0 0 2 &ipic 15 8
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a800 0 0 3 &ipic 16 8
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a800 0 0 4 &ipic 17 8
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/* IDSEL 0x16 AD22*/
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b000 0 0 1 &ipic 17 8
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b000 0 0 2 &ipic 14 8
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b000 0 0 3 &ipic 15 8
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b000 0 0 4 &ipic 16 8
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/* IDSEL 0x17 AD23*/
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b800 0 0 1 &ipic 16 8
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b800 0 0 2 &ipic 17 8
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b800 0 0 3 &ipic 14 8
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b800 0 0 4 &ipic 15 8
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/* IDSEL 0x18 AD24*/
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c000 0 0 1 &ipic 15 8
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c000 0 0 2 &ipic 16 8
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c000 0 0 3 &ipic 17 8
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c000 0 0 4 &ipic 14 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 d0000000 0 00100000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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@ -335,4 +276,63 @@
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interrupt-parent = < &ipic >;
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};
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};
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pci@e0008500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 AD17 */
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8800 0 0 1 &ipic 14 8
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8800 0 0 2 &ipic 15 8
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8800 0 0 3 &ipic 16 8
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8800 0 0 4 &ipic 17 8
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/* IDSEL 0x12 AD18 */
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9000 0 0 1 &ipic 16 8
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9000 0 0 2 &ipic 17 8
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9000 0 0 3 &ipic 14 8
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9000 0 0 4 &ipic 15 8
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/* IDSEL 0x13 AD19 */
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9800 0 0 1 &ipic 17 8
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9800 0 0 2 &ipic 14 8
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9800 0 0 3 &ipic 15 8
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9800 0 0 4 &ipic 16 8
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/* IDSEL 0x15 AD21*/
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a800 0 0 1 &ipic 14 8
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a800 0 0 2 &ipic 15 8
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a800 0 0 3 &ipic 16 8
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a800 0 0 4 &ipic 17 8
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/* IDSEL 0x16 AD22*/
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b000 0 0 1 &ipic 17 8
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b000 0 0 2 &ipic 14 8
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b000 0 0 3 &ipic 15 8
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b000 0 0 4 &ipic 16 8
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/* IDSEL 0x17 AD23*/
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b800 0 0 1 &ipic 16 8
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b800 0 0 2 &ipic 17 8
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b800 0 0 3 &ipic 14 8
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b800 0 0 4 &ipic 15 8
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/* IDSEL 0x18 AD24*/
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c000 0 0 1 &ipic 15 8
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c000 0 0 2 &ipic 16 8
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c000 0 0 3 &ipic 17 8
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c000 0 0 4 &ipic 14 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 d0000000 0 00100000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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@ -92,39 +92,6 @@
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descriptor-types-mask = <0122003f>;
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};
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pci@8500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x10 AD16 (USB) */
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8000 0 0 1 &pic 11 8
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/* IDSEL 0x11 AD17 (Mini1)*/
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8800 0 0 1 &pic 12 8
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8800 0 0 2 &pic 13 8
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8800 0 0 3 &pic 14 8
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8800 0 0 4 &pic 30 8
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/* IDSEL 0x12 AD18 (PCI/Mini2) */
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9000 0 0 1 &pic 13 8
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9000 0 0 2 &pic 14 8
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9000 0 0 3 &pic 30 8
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9000 0 0 4 &pic 11 8>;
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interrupt-parent = <&pic>;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 10000000
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02000000 0 90000000 90000000 0 10000000
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01000000 0 d0000000 d0000000 0 04000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
|
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#size-cells = <2>;
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#address-cells = <3>;
|
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reg = <8500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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pic:pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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|
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@ -294,4 +261,37 @@
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interrupt-parent = <&pic>;
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};
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||||
};
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|
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pci@e0008500 {
|
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interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 AD16 (USB) */
|
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8000 0 0 1 &pic 11 8
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|
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/* IDSEL 0x11 AD17 (Mini1)*/
|
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8800 0 0 1 &pic 12 8
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8800 0 0 2 &pic 13 8
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8800 0 0 3 &pic 14 8
|
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8800 0 0 4 &pic 30 8
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|
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/* IDSEL 0x12 AD18 (PCI/Mini2) */
|
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9000 0 0 1 &pic 13 8
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9000 0 0 2 &pic 14 8
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9000 0 0 3 &pic 30 8
|
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9000 0 0 4 &pic 11 8>;
|
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|
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interrupt-parent = <&pic>;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 d0000000 d0000000 0 04000000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -178,52 +178,6 @@
|
|||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
pci@8500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 - SATA */
|
||||
8000 0 0 1 &ipic 16 8 /* SATA_INTA */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@8600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E - MiniPCI Slot */
|
||||
7000 0 0 1 &ipic 15 8 /* PCI_INTA */
|
||||
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <1 1>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8600 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
|
|
@ -245,4 +199,53 @@
|
|||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 - SATA */
|
||||
8000 0 0 1 &ipic 16 8 /* SATA_INTA */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E - MiniPCI Slot */
|
||||
7000 0 0 1 &ipic 15 8 /* PCI_INTA */
|
||||
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008600 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -134,28 +134,6 @@
|
|||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
pci@8600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <1 1>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8600 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
|
|
@ -177,4 +155,26 @@
|
|||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <1 1>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008600 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -183,7 +183,38 @@
|
|||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
pci@8500 {
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -238,12 +269,12 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8500 100>;
|
||||
reg = <e0008500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@8600 {
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -298,39 +329,8 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8600 100>;
|
||||
reg = <e0008600 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -111,66 +111,6 @@
|
|||
descriptor-types-mask = <01010ebf>;
|
||||
};
|
||||
|
||||
pci@8500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 AD17 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
|
||||
/* IDSEL 0x12 AD18 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
|
||||
/* IDSEL 0x13 AD19 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
|
||||
/* IDSEL 0x15 AD21*/
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
|
||||
/* IDSEL 0x16 AD22*/
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
|
||||
/* IDSEL 0x17 AD23*/
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
|
||||
/* IDSEL 0x18 AD24*/
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
|
@ -365,6 +305,65 @@
|
|||
interrupts = <20 8 21 8>; //high:32 low:33
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 AD17 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
|
||||
/* IDSEL 0x12 AD18 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
|
||||
/* IDSEL 0x13 AD19 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
|
||||
/* IDSEL 0x15 AD21*/
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
|
||||
/* IDSEL 0x16 AD22*/
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
|
||||
/* IDSEL 0x17 AD23*/
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
|
||||
/* IDSEL 0x18 AD24*/
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -171,7 +171,19 @@
|
|||
interrupts = <2a 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
pci@8000 {
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -255,20 +267,8 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <e0008000 1000>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00100000>; // CCSRBAR 1M
|
||||
reg = <e0000000 00001000>; // CCSRBAR 1M
|
||||
bus-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
|
|
@ -135,7 +135,19 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
pci1: pci@8000 {
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pci@e0008000 {
|
||||
interrupt-map-mask = <1f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -190,7 +202,7 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <e0008000 1000>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
|
||||
|
|
@ -206,7 +218,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pci@9000 {
|
||||
pci@e0009000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -224,20 +236,8 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <9000 1000>;
|
||||
reg = <e0009000 1000>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,16 +43,7 @@
|
|||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
|
||||
|
||||
ranges = <00001000 e0001000 000ff000
|
||||
80000000 80000000 20000000
|
||||
a0000000 a0000000 10000000
|
||||
b0000000 b0000000 00100000
|
||||
c0000000 c0000000 20000000
|
||||
b0100000 b0100000 00100000
|
||||
e1000000 e1000000 00010000
|
||||
e1010000 e1010000 00010000
|
||||
e1020000 e1020000 00010000>;
|
||||
ranges = <00000000 e0000000 00100000>;
|
||||
reg = <e0000000 00001000>; // CCSRBAR 1M
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
|
|
@ -147,7 +138,25 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
pci@8000 {
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <e0000 1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
|
|
@ -175,16 +184,16 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <e0008000 1000>;
|
||||
};
|
||||
|
||||
pcie@9000 {
|
||||
pcie@e0009000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <9000 1000>;
|
||||
reg = <e0009000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e1010000 0 00010000>;
|
||||
|
|
@ -199,15 +208,28 @@
|
|||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 80000000
|
||||
02000000 0 80000000
|
||||
0 20000000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@a000 {
|
||||
pcie@e000a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <a000 1000>;
|
||||
reg = <e000a000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 e1020000 0 00010000>;
|
||||
|
|
@ -222,15 +244,28 @@
|
|||
0000 0 0 3 &mpic 2 1
|
||||
0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 10000000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@b000 {
|
||||
pcie@e000b000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <b000 1000>;
|
||||
reg = <e000b000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 b0000000 b0000000 0 00100000
|
||||
01000000 0 00000000 b0100000 0 00100000>;
|
||||
|
|
@ -256,6 +291,20 @@
|
|||
f800 0 0 0 &i8259 e 2
|
||||
f900 0 0 0 &i8259 5 2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 b0000000
|
||||
02000000 0 b0000000
|
||||
0 00100000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
|
||||
uli1575@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -263,21 +312,10 @@
|
|||
ranges = <02000000 0 b0000000
|
||||
02000000 0 b0000000
|
||||
0 00100000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
|
||||
pci_bridge@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
ranges = <02000000 0 b0000000
|
||||
02000000 0 b0000000
|
||||
0 00100000
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -333,22 +371,4 @@
|
|||
};
|
||||
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <e0000 1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,13 +42,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <00001000 e0001000 000ff000
|
||||
80000000 80000000 10000000
|
||||
e2000000 e2000000 00800000
|
||||
90000000 90000000 10000000
|
||||
e2800000 e2800000 00800000
|
||||
a0000000 a0000000 20000000
|
||||
e3000000 e3000000 01000000>;
|
||||
ranges = <00000000 e0000000 00100000>;
|
||||
reg = <e0000000 00001000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
|
|
@ -187,7 +181,19 @@
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
pci@8000 {
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x4 (PCIX Slot 2) */
|
||||
|
|
@ -259,7 +265,7 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <e0008000 1000>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
|
||||
|
|
@ -336,7 +342,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pci@9000 {
|
||||
pci@e0009000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -355,12 +361,12 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <9000 1000>;
|
||||
reg = <e0009000 1000>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
/* PCI Express */
|
||||
pcie@a000 {
|
||||
|
||||
pcie@e000a000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -379,20 +385,21 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <a000 1000>;
|
||||
reg = <e000a000 1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
};
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 20000000
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00100000>; // CCSRBAR 1M
|
||||
reg = <e0000000 00001000>; // CCSRBAR 1M
|
||||
bus-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
|
|
@ -135,7 +135,19 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
pci1: pci@8000 {
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pci@e0008000 {
|
||||
interrupt-map-mask = <1f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -190,7 +202,7 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <e0008000 1000>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
|
||||
|
|
@ -206,7 +218,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
pci@9000 {
|
||||
pci@e0009000 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -224,20 +236,8 @@
|
|||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <9000 1000>;
|
||||
reg = <e0009000 1000>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -130,96 +130,6 @@
|
|||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
pci@8000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <8000 1000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x2 */
|
||||
1000 0 0 1 &mpic 1 1
|
||||
1000 0 0 2 &mpic 2 1
|
||||
1000 0 0 3 &mpic 3 1
|
||||
1000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 0x3 */
|
||||
1800 0 0 1 &mpic 4 1
|
||||
1800 0 0 2 &mpic 1 1
|
||||
1800 0 0 3 &mpic 2 1
|
||||
1800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 0x4 */
|
||||
2000 0 0 1 &mpic 3 1
|
||||
2000 0 0 2 &mpic 4 1
|
||||
2000 0 0 3 &mpic 1 1
|
||||
2000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x5 */
|
||||
2800 0 0 1 &mpic 2 1
|
||||
2800 0 0 2 &mpic 3 1
|
||||
2800 0 0 3 &mpic 4 1
|
||||
2800 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 12 */
|
||||
6000 0 0 1 &mpic 1 1
|
||||
6000 0 0 2 &mpic 2 1
|
||||
6000 0 0 3 &mpic 3 1
|
||||
6000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 13 */
|
||||
6800 0 0 1 &mpic 4 1
|
||||
6800 0 0 2 &mpic 1 1
|
||||
6800 0 0 3 &mpic 2 1
|
||||
6800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 14*/
|
||||
7000 0 0 1 &mpic 3 1
|
||||
7000 0 0 2 &mpic 4 1
|
||||
7000 0 0 3 &mpic 1 1
|
||||
7000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 15 */
|
||||
7800 0 0 1 &mpic 2 1
|
||||
7800 0 0 2 &mpic 3 1
|
||||
7800 0 0 3 &mpic 4 1
|
||||
7800 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 18 */
|
||||
9000 0 0 1 &mpic 1 1
|
||||
9000 0 0 2 &mpic 2 1
|
||||
9000 0 0 3 &mpic 3 1
|
||||
9000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 19 */
|
||||
9800 0 0 1 &mpic 4 1
|
||||
9800 0 0 2 &mpic 1 1
|
||||
9800 0 0 3 &mpic 2 1
|
||||
9800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 20 */
|
||||
a000 0 0 1 &mpic 3 1
|
||||
a000 0 0 2 &mpic 4 1
|
||||
a000 0 0 3 &mpic 1 1
|
||||
a000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 21 */
|
||||
a800 0 0 1 &mpic 2 1
|
||||
a800 0 0 2 &mpic 3 1
|
||||
a800 0 0 3 &mpic 4 1
|
||||
a800 0 0 4 &mpic 1 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
|
@ -319,4 +229,94 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <e0008000 1000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x2 */
|
||||
1000 0 0 1 &mpic 1 1
|
||||
1000 0 0 2 &mpic 2 1
|
||||
1000 0 0 3 &mpic 3 1
|
||||
1000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 0x3 */
|
||||
1800 0 0 1 &mpic 4 1
|
||||
1800 0 0 2 &mpic 1 1
|
||||
1800 0 0 3 &mpic 2 1
|
||||
1800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 0x4 */
|
||||
2000 0 0 1 &mpic 3 1
|
||||
2000 0 0 2 &mpic 4 1
|
||||
2000 0 0 3 &mpic 1 1
|
||||
2000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x5 */
|
||||
2800 0 0 1 &mpic 2 1
|
||||
2800 0 0 2 &mpic 3 1
|
||||
2800 0 0 3 &mpic 4 1
|
||||
2800 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 12 */
|
||||
6000 0 0 1 &mpic 1 1
|
||||
6000 0 0 2 &mpic 2 1
|
||||
6000 0 0 3 &mpic 3 1
|
||||
6000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 13 */
|
||||
6800 0 0 1 &mpic 4 1
|
||||
6800 0 0 2 &mpic 1 1
|
||||
6800 0 0 3 &mpic 2 1
|
||||
6800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 14*/
|
||||
7000 0 0 1 &mpic 3 1
|
||||
7000 0 0 2 &mpic 4 1
|
||||
7000 0 0 3 &mpic 1 1
|
||||
7000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 15 */
|
||||
7800 0 0 1 &mpic 2 1
|
||||
7800 0 0 2 &mpic 3 1
|
||||
7800 0 0 3 &mpic 4 1
|
||||
7800 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 18 */
|
||||
9000 0 0 1 &mpic 1 1
|
||||
9000 0 0 2 &mpic 2 1
|
||||
9000 0 0 3 &mpic 3 1
|
||||
9000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 19 */
|
||||
9800 0 0 1 &mpic 4 1
|
||||
9800 0 0 2 &mpic 1 1
|
||||
9800 0 0 3 &mpic 2 1
|
||||
9800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 20 */
|
||||
a000 0 0 1 &mpic 3 1
|
||||
a000 0 0 2 &mpic 4 1
|
||||
a000 0 0 3 &mpic 1 1
|
||||
a000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 21 */
|
||||
a800 0 0 1 &mpic 2 1
|
||||
a800 0 0 2 &mpic 3 1
|
||||
a800 0 0 3 &mpic 4 1
|
||||
a800 0 0 4 &mpic 1 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,11 +53,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <00001000 f8001000 000ff000
|
||||
80000000 80000000 20000000
|
||||
e2000000 e2000000 00100000
|
||||
a0000000 a0000000 20000000
|
||||
e3000000 e3000000 00100000>;
|
||||
ranges = <00000000 f8000000 00100000>;
|
||||
reg = <f8000000 00001000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
|
|
@ -208,13 +204,25 @@
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
pcie@8000 {
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@f8008000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8000 1000>;
|
||||
reg = <f8008000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
|
|
@ -252,6 +260,19 @@
|
|||
f800 0 0 0 &i8259 e 2
|
||||
f900 0 0 0 &i8259 5 2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 80000000
|
||||
02000000 0 80000000
|
||||
0 20000000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
uli1575@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -262,18 +283,6 @@
|
|||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
|
||||
pci_bridge@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
ranges = <02000000 0 80000000
|
||||
02000000 0 80000000
|
||||
0 20000000
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -294,8 +303,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <9 2>;
|
||||
interrupt-parent =
|
||||
<&mpic>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i8042@60 {
|
||||
|
|
@ -332,13 +340,13 @@
|
|||
|
||||
};
|
||||
|
||||
pcie@9000 {
|
||||
pcie@f8009000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <9000 1000>;
|
||||
reg = <f8009000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 20000000
|
||||
01000000 0 00000000 e3000000 0 00100000>;
|
||||
|
|
@ -353,17 +361,18 @@
|
|||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
};
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 20000000
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
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