From 1b5d3e00d45e093fa0551c588034c3355b362f66 Mon Sep 17 00:00:00 2001 From: Jiang Liu Date: Mon, 9 Jun 2014 16:19:56 +0800 Subject: [PATCH] x86, SFI, irq: Provide basic irqdomain support Enhance SFI to provide basic support of irqdomain with identity mapping between GSIs and IRQs. Some Intel MID platforms assumes identity mapping between GSI and IRQ, so we can't dynamically allocate IRQ number on demand. Signed-off-by: Jiang Liu Cc: Konrad Rzeszutek Wilk Cc: Tony Luck Cc: Joerg Roedel Cc: Paul Gortmaker Cc: Greg Kroah-Hartman Cc: H. Peter Anvin Cc: sfi-devel@simplefirmware.org Cc: Benjamin Herrenschmidt Cc: Grant Likely Cc: Rafael J. Wysocki Cc: Bjorn Helgaas Cc: Randy Dunlap Cc: Yinghai Lu Cc: Len Brown Cc: David Cohen Cc: Kuppuswamy Sathyanarayanan Link: http://lkml.kernel.org/r/1402302011-23642-28-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner --- arch/x86/pci/intel_mid_pci.c | 3 +++ arch/x86/platform/intel-mid/sfi.c | 2 ++ arch/x86/platform/sfi/sfi.c | 8 +++++++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 84b9d672843d..fcbdc5fac2c6 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -217,6 +217,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to * IOAPIC RTE entries, so we just enable RTE for the device. */ + if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0) + return -EBUSY; + irq_attr.ioapic = mp_find_ioapic(dev->irq); irq_attr.ioapic_pin = dev->irq; irq_attr.trigger = 1; /* level */ diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c index 994c40bd7cb7..7161395e7de7 100644 --- a/arch/x86/platform/intel-mid/sfi.c +++ b/arch/x86/platform/intel-mid/sfi.c @@ -473,6 +473,8 @@ static int __init sfi_parse_devs(struct sfi_table_header *table) /* PNW and CLV go with active low */ irq_attr.polarity = 1; } + WARN_ON(mp_map_gsi_to_irq(irq, + IOAPIC_MAP_ALLOC) < 0); io_apic_set_pci_routing(NULL, irq, &irq_attr); } } else { diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c index 8f2f789c6f04..1fdaa57f41a5 100644 --- a/arch/x86/platform/sfi/sfi.c +++ b/arch/x86/platform/sfi/sfi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -70,19 +71,24 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table) #endif /* CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_X86_IO_APIC +static struct irq_domain_ops sfi_ioapic_irqdomain_ops; static int __init sfi_parse_ioapic(struct sfi_table_header *table) { struct sfi_table_simple *sb; struct sfi_apic_table_entry *pentry; int i, num; + struct ioapic_domain_cfg cfg = { + .type = IOAPIC_DOMAIN_STRICT, + .ops = &sfi_ioapic_irqdomain_ops, + }; sb = (struct sfi_table_simple *)table; num = SFI_GET_NUM_ENTRIES(sb, struct sfi_apic_table_entry); pentry = (struct sfi_apic_table_entry *)sb->pentry; for (i = 0; i < num; i++) { - mp_register_ioapic(i, pentry->phys_addr, gsi_top, NULL); + mp_register_ioapic(i, pentry->phys_addr, gsi_top, &cfg); pentry++; }