ARM: LPAE: MMU setup for the 3-level page table format
This patch adds the MMU initialisation for the LPAE page table format. The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new proc-v7-3level.S file contains the TTB initialisation, context switch and PTE setting code with the LPAE. The TTBRx split is based on the PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings (supersections) and a few other memory types in mmu.c are conditionally compiled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas
Родитель
da02877987
Коммит
1b6ba46b7e
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@ -39,8 +39,14 @@
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#error KERNEL_RAM_VADDR must start at 0xXXXX8000
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#endif
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#ifdef CONFIG_ARM_LPAE
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/* LPAE requires an additional page for the PGD */
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#define PG_DIR_SIZE 0x5000
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#define PMD_ORDER 3
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#else
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#define PG_DIR_SIZE 0x4000
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#define PMD_ORDER 2
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
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@ -164,6 +170,25 @@ __create_page_tables:
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teq r0, r6
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bne 1b
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#ifdef CONFIG_ARM_LPAE
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/*
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* Build the PGD table (first level) to point to the PMD table. A PGD
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* entry is 64-bit wide.
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*/
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mov r0, r4
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add r3, r4, #0x1000 @ first PMD table address
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orr r3, r3, #3 @ PGD block type
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mov r6, #4 @ PTRS_PER_PGD
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mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
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1: str r3, [r0], #4 @ set bottom PGD entry bits
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str r7, [r0], #4 @ set top PGD entry bits
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add r3, r3, #0x1000 @ next PMD table
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subs r6, r6, #1
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bne 1b
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add r4, r4, #0x1000 @ point to the PMD tables
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#endif
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ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
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/*
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@ -219,8 +244,8 @@ __create_page_tables:
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#endif
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/*
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* Then map boot params address in r2 or
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* the first 1MB of ram if boot params address is not specified.
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* Then map boot params address in r2 or the first 1MB (2MB with LPAE)
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* of ram if boot params address is not specified.
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*/
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mov r0, r2, lsr #SECTION_SHIFT
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movs r0, r0, lsl #SECTION_SHIFT
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@ -251,7 +276,15 @@ __create_page_tables:
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mov r3, r7, lsr #SECTION_SHIFT
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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orr r3, r7, r3, lsl #SECTION_SHIFT
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#ifdef CONFIG_ARM_LPAE
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mov r7, #1 << (54 - 32) @ XN
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#else
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orr r3, r3, #PMD_SECT_XN
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#endif
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1: str r3, [r0], #4
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#ifdef CONFIG_ARM_LPAE
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str r7, [r0], #4
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#endif
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add r3, r3, #1 << SECTION_SHIFT
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cmp r0, r6
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blo 1b
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@ -282,6 +315,9 @@ __create_page_tables:
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add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
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str r3, [r0]
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#endif
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#endif
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#ifdef CONFIG_ARM_LPAE
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sub r4, r4, #0x1000 @ point to the PGD table
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#endif
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mov pc, lr
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ENDPROC(__create_page_tables)
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@ -374,12 +410,17 @@ __enable_mmu:
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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#ifdef CONFIG_ARM_LPAE
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mov r5, #0
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mcrr p15, 0, r4, r5, c2 @ load TTBR0
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#else
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mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT))
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mcr p15, 0, r5, c3, c0, 0 @ load domain access register
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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#endif
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b __turn_mmu_on
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ENDPROC(__enable_mmu)
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@ -150,6 +150,7 @@ static int __init early_nowrite(char *__unused)
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}
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early_param("nowb", early_nowrite);
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#ifndef CONFIG_ARM_LPAE
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static int __init early_ecc(char *p)
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{
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if (memcmp(p, "on", 2) == 0)
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@ -159,6 +160,7 @@ static int __init early_ecc(char *p)
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return 0;
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}
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early_param("ecc", early_ecc);
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#endif
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static int __init noalign_setup(char *__unused)
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{
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@ -228,10 +230,12 @@ static struct mem_type mem_types[] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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.domain = DOMAIN_KERNEL,
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},
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#ifndef CONFIG_ARM_LPAE
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[MT_MINICLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
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.domain = DOMAIN_KERNEL,
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},
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#endif
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[MT_LOW_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_RDONLY,
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@ -429,6 +433,7 @@ static void __init build_mem_type_table(void)
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* ARMv6 and above have extended page tables.
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*/
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if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
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#ifndef CONFIG_ARM_LPAE
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/*
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* Mark cache clean areas and XIP ROM read only
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* from SVC mode and no access from userspace.
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@ -436,6 +441,7 @@ static void __init build_mem_type_table(void)
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mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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#endif
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if (is_smp()) {
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/*
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@ -474,6 +480,18 @@ static void __init build_mem_type_table(void)
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mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
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}
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#ifdef CONFIG_ARM_LPAE
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/*
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* Do not generate access flag faults for the kernel mappings.
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*/
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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mem_types[i].prot_pte |= PTE_EXT_AF;
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mem_types[i].prot_sect |= PMD_SECT_AF;
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}
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kern_pgprot |= PTE_EXT_AF;
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vecs_pgprot |= PTE_EXT_AF;
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#endif
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for (i = 0; i < 16; i++) {
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unsigned long v = pgprot_val(protection_map[i]);
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protection_map[i] = __pgprot(v | user_pgprot);
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@ -572,8 +590,10 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
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if (((addr | end | phys) & ~SECTION_MASK) == 0) {
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pmd_t *p = pmd;
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#ifndef CONFIG_ARM_LPAE
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if (addr & SECTION_SIZE)
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pmd++;
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#endif
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do {
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*pmd = __pmd(phys | type->prot_sect);
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@ -603,6 +623,7 @@ static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
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} while (pud++, addr = next, addr != end);
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}
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#ifndef CONFIG_ARM_LPAE
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static void __init create_36bit_mapping(struct map_desc *md,
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const struct mem_type *type)
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{
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@ -662,6 +683,7 @@ static void __init create_36bit_mapping(struct map_desc *md,
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pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
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} while (addr != end);
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}
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#endif /* !CONFIG_ARM_LPAE */
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/*
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* Create the page directory entries and any necessary
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@ -693,6 +715,7 @@ static void __init create_mapping(struct map_desc *md)
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type = &mem_types[md->type];
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#ifndef CONFIG_ARM_LPAE
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/*
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* Catch 36-bit addresses
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*/
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@ -700,6 +723,7 @@ static void __init create_mapping(struct map_desc *md)
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create_36bit_mapping(md, type);
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return;
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}
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#endif
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addr = md->virtual & PAGE_MASK;
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phys = __pfn_to_phys(md->pfn);
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@ -897,7 +921,13 @@ static inline void prepare_page_table(void)
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pmd_clear(pmd_off_k(addr));
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}
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#ifdef CONFIG_ARM_LPAE
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/* the first page is reserved for pgd */
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#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
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PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
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#else
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#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
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#endif
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/*
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* Reserve the special regions of memory
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@ -91,8 +91,9 @@
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#if L_PTE_SHARED != PTE_EXT_SHARED
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#error PTE shared bit mismatch
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#endif
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#if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
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L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
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#if !defined (CONFIG_ARM_LPAE) && \
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(L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
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L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
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#error Invalid Linux PTE bit settings
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#endif
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#endif /* CONFIG_MMU */
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@ -0,0 +1,150 @@
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/*
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* arch/arm/mm/proc-v7-3level.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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* based on arch/arm/mm/proc-v7-2level.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define TTB_IRGN_NC (0 << 8)
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#define TTB_IRGN_WBWA (1 << 8)
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#define TTB_IRGN_WT (2 << 8)
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#define TTB_IRGN_WB (3 << 8)
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#define TTB_RGN_NC (0 << 10)
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#define TTB_RGN_OC_WBWA (1 << 10)
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#define TTB_RGN_OC_WT (2 << 10)
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#define TTB_RGN_OC_WB (3 << 10)
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#define TTB_S (3 << 12)
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#define TTB_EAE (1 << 31)
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB)
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#define PMD_FLAGS_UP (PMD_SECT_WB)
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
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#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S)
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys (physical address of
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* the new TTB).
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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and r3, r1, #0xff
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mov r3, r3, lsl #(48 - 32) @ ASID
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mcrr p15, 0, r0, r3, c2 @ set TTB 0
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isb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_switch_mm)
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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* - ptep - pointer to level 3 translation table entry
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* - pte - PTE value to store (64-bit in r2 and r3)
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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tst r2, #L_PTE_PRESENT
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beq 1f
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tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
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orreq r2, #L_PTE_RDONLY
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1: strd r2, r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_set_pte_ext)
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/*
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* Memory region attributes for LPAE (defined in pgtable-3level.h):
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*
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* n = AttrIndx[2:0]
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*
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* n MAIR
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* UNCACHED 000 00000000
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* BUFFERABLE 001 01000100
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* DEV_WC 001 01000100
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* WRITETHROUGH 010 10101010
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* WRITEBACK 011 11101110
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* DEV_CACHED 011 11101110
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* DEV_SHARED 100 00000100
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* DEV_NONSHARED 100 00000100
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* unused 101
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* unused 110
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* WRITEALLOC 111 11111111
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*/
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.equ PRRR, 0xeeaa4400 @ MAIR0
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.equ NMRR, 0xff000004 @ MAIR1
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/*
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* Macro for setting up the TTBRx and TTBCR registers.
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* - \ttbr1 updated.
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*/
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.macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
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ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
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cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
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mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register
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orr \tmp, \tmp, #TTB_EAE
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
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/*
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* TTBR0/TTBR1 split (PAGE_OFFSET):
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* 0x40000000: T0SZ = 2, T1SZ = 0 (not used)
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* 0x80000000: T0SZ = 0, T1SZ = 1
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* 0xc0000000: T0SZ = 0, T1SZ = 2
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*
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* Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
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* booting secondary CPUs would end up using TTBR1 for the identity
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* mapping set up in TTBR0.
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*/
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bhi 9001f @ PHYS_OFFSET > PAGE_OFFSET?
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orr \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
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#if defined CONFIG_VMSPLIT_2G
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/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
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add \ttbr1, \ttbr1, #1 << 4 @ skip two L1 entries
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#elif defined CONFIG_VMSPLIT_3G
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/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
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add \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
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#endif
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/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
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9001: mcr p15, 0, \tmp, c2, c0, 2 @ TTB control register
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mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
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.endm
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__CPUINIT
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/*
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* AT
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* TFR EV X F IHD LR S
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* .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
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* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 11 0 110 1 0011 1100 .111 1101 < we want
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*/
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.align 2
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
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.previous
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@ -19,7 +19,11 @@
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#include "proc-macros.S"
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#ifdef CONFIG_ARM_LPAE
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#include "proc-v7-3level.S"
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#else
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#include "proc-v7-2level.S"
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#endif
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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@ -87,7 +91,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 7
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.equ cpu_v7_suspend_size, 4 * 8
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r10, lr}
|
||||
|
|
@ -96,10 +100,11 @@ ENTRY(cpu_v7_do_suspend)
|
|||
stmia r0!, {r4 - r5}
|
||||
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
mrc p15, 0, r7, c2, c0, 1 @ TTB 1
|
||||
mrc p15, 0, r11, c2, c0, 2 @ TTB control register
|
||||
mrc p15, 0, r8, c1, c0, 0 @ Control register
|
||||
mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
|
||||
mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
|
||||
stmia r0, {r6 - r10}
|
||||
stmia r0, {r6 - r11}
|
||||
ldmfd sp!, {r4 - r10, pc}
|
||||
ENDPROC(cpu_v7_do_suspend)
|
||||
|
||||
|
|
@ -111,13 +116,15 @@ ENTRY(cpu_v7_do_resume)
|
|||
ldmia r0!, {r4 - r5}
|
||||
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
|
||||
ldmia r0, {r6 - r10}
|
||||
ldmia r0, {r6 - r11}
|
||||
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
|
||||
ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
|
||||
#endif
|
||||
mcr p15, 0, r1, c2, c0, 0 @ TTB 0
|
||||
mcr p15, 0, r7, c2, c0, 1 @ TTB 1
|
||||
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
|
||||
mcr p15, 0, r11, c2, c0, 2 @ TTB control register
|
||||
mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
|
||||
teq r4, r9 @ Is it already set?
|
||||
mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
|
||||
|
|
@ -291,11 +298,11 @@ __v7_setup_stack:
|
|||
*/
|
||||
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
|
||||
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
|
||||
PMD_FLAGS_SMP | \mm_mmuflags)
|
||||
PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
|
||||
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
|
||||
PMD_FLAGS_UP | \mm_mmuflags)
|
||||
.long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ | \io_mmuflags
|
||||
PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
|
||||
.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
|
||||
W(b) \initfunc
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
|
|
@ -308,6 +315,7 @@ __v7_setup_stack:
|
|||
.long v7_cache_fns
|
||||
.endm
|
||||
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
/*
|
||||
* ARM Ltd. Cortex A5 processor.
|
||||
*/
|
||||
|
|
@ -327,6 +335,7 @@ __v7_ca9mp_proc_info:
|
|||
.long 0xff0ffff0
|
||||
__v7_proc __v7_ca9mp_setup
|
||||
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
|
||||
#endif /* CONFIG_ARM_LPAE */
|
||||
|
||||
/*
|
||||
* ARM Ltd. Cortex A15 processor.
|
||||
|
|
|
|||
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